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公开(公告)号：US12105139B2
公开(公告)日：2024-10-01
申请号：US17565284
申请日：2021-12-29
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3183
CPC分类号： G01R31/287 , G01R31/2879 , G01R31/31718 , G01R31/318314
摘要： A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.
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公开(公告)号：US12038472B2
公开(公告)日：2024-07-16
申请号：US16742121
申请日：2020-01-14
发明人： Naoya Toyota , Yasuki Akita
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/287 , G01R31/31907 , G01R31/31935
摘要： A test site includes: at least one test module that tests a device under test; and a waveform data acquisition module that converts an electrical signal relating to the DUT into a digital signal with a predetermined sampling rate so as to acquire waveform data in the form of a digital signal sequence. The higher-level controller controls the at least one test module and the waveform data acquisition module, and collects the waveform data acquired by the waveform data acquisition module in a form associated with the operation state of the at least one test module.
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公开(公告)号：US20240094284A1
公开(公告)日：2024-03-21
申请号：US18053411
申请日：2022-11-08
申请人： NXP B.V.
IPC分类号： G01R31/28
CPC分类号： G01R31/2882 , G01R31/287
摘要： Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.
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公开(公告)号：US11733292B2
公开(公告)日：2023-08-22
申请号：US17412889
申请日：2021-08-26
发明人： Ba Duong Phan , Alireza Daneshgar
CPC分类号： G01R31/287 , G01R1/04 , G01R1/44
摘要： A testing apparatus for Devices Under Test (DUTs) includes at least one intake damper and at least one exhaust damper. At least one fan moves recirculated fluid and exterior fluid across one or more DUTs inside the testing apparatus. In one aspect, the testing apparatus includes a door to provide access to a chamber and the door includes at least one channel. At least a portion of the fluid flows through the at least one channel of the door. In another aspect, the door is configured to provide access to a chamber from the front of the chamber and the fluid is moved in a direction across the one or more DUTs substantially from the front of the chamber towards a rear of the chamber.
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公开(公告)号：US20230251305A1
公开(公告)日：2023-08-10
申请号：US17608632
申请日：2020-12-30
发明人： Teck Huat TAN , Chun Hong LOW
IPC分类号： G01R31/28
CPC分类号： G01R31/2867 , G01R31/2862 , G01R31/2863 , G01R31/287
摘要： The present disclosure relates to burn-in apparatus, transfer method, burn-in chamber, and interchangeable frame thereof for semiconductor devices burn-in process. The burn-in apparatus comprises of a burn-in chamber with an incomplete base which is adapted to be completed and thermally insulated in cooperation with a thermal insulation base of at least one interchangeable frame which is adapted to be removably moved into and docked in the burn-in chamber to complete the burn-in apparatus. The burn-in apparatus comprises the burn-in chamber and at least one frame. The apparatus is complete and thermally insulated when the frame is moved into the burn-in chamber and docked therein. The apparatus is incomplete and thermally uninsulated when the frame is moved out of the burn-in chamber and undocked therefrom.
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公开(公告)号：US20180364302A1
公开(公告)日：2018-12-20
申请号：US15623366
申请日：2017-06-14
发明人： Long Chieu
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/2894 , G01R31/287 , G01R31/31707 , G01R31/31718
摘要： A method for testing a plurality of electronic devices includes performing tests of up to m devices at a time to measure device parameters on a device tester configured to test up to m devices at a time, where m is an integer. After each test, the method includes performing statistical analysis of the measured device parameters for all tested devices to determine statistical data, including updated mean and standard deviation for each parameter, and storing only the statistical data, and not the measured device parameters. The method further includes determining new pass/fail limits for each device parameter based on the updated mean and standard deviation, and determining pass or fail of each device based on the new pass/fail limits for each device parameter.
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公开(公告)号：US20180313891A1
公开(公告)日：2018-11-01
申请号：US15582137
申请日：2017-04-28
发明人： Rotem Nahum , Rebecca Toy , Boilam Phan , Jungtsung Liu , Leon Chen
IPC分类号： G01R31/28
CPC分类号： G01R31/2834 , G01R31/287
摘要： A system for performing an automated test is disclosed. The system comprises a user computer operable to load a test program from a user to a control server, wherein the test program comprises a plurality of test flows. The system further comprises a tester deploying a plurality of primitives. Further, the control server is communicatively coupled to the user computer and to the tester, wherein the control server is operable to download the test program to a primitive from the plurality of primitives, and wherein the control server is further operable to execute a first test flow from the plurality of test flows on a first DUT within the primitive and concurrently execute a second test flow from the plurality of test flows on a second DUT within the primitive.
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公开(公告)号：US10018668B2
公开(公告)日：2018-07-10
申请号：US15713111
申请日：2017-09-22
发明人： Hoi Hin Loo , Soh Ying Seah
IPC分类号： G01R31/28
CPC分类号： G01R31/2851 , G01R31/2853 , G01R31/287 , G01R31/2894
摘要： A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.
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公开(公告)号：US09921264B2
公开(公告)日：2018-03-20
申请号：US15133666
申请日：2016-04-20
发明人： Andrew A. Turner , Hunter Feng Shi
IPC分类号： G01R31/28
CPC分类号： G01R31/2851 , G01R31/287
摘要： In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.
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公开(公告)号：US09870959B1
公开(公告)日：2018-01-16
申请号：US13651288
申请日：2012-10-12
申请人： Altera Corporation
发明人： Nagesh Vodrahalli
CPC分类号： H01L22/14 , G01R31/287 , G01R31/2886 , H01L22/32 , H01L22/34 , H05K13/0465
摘要： Techniques for electrically testing a flip-chip assembly during its manufacture include a flip-chip assembly having an integrated circuit (IC) die and an IC package substrate. The IC package substrate is placed on a substrate part holder that includes test sockets and heating elements. The IC die is then placed on the placed IC package substrate. The placed IC die and IC package substrate are aligned such that conductive contacts are formed from conductive bumps and pads deposited on the surface of the IC die and IC package substrate. While the bumps and pads are in conductive contact, but prior to attachment, the flip-chip assembly is electrically tested. If the flip-chip assembly passes electrical testing, the conductive contacts may be attached by the heating elements on the substrate part holder, such as in a solder reflow process when the bumps are made from solder.
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