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    ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA
    1.
    发明申请
    ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA 有权
    集成电路设计在不影响区域的可靠性

    公开(公告)号：US20100199252A1

    公开(公告)日：2010-08-05

    申请号：US12364649

    申请日：2009-02-03

    申请人： Pavan Vithal Torvi ,  Girishankar Gurumurthy ,  Dharin N. Shah ,  Ajith Harihara Subramonia

    发明人： Pavan Vithal Torvi ,  Girishankar Gurumurthy ,  Dharin N. Shah ,  Ajith Harihara Subramonia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Improving the routability of integrated circuit (IC) design without impacting the area. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.

    摘要翻译： 提高集成电路（IC）设计的可布线性，而不影响该区域。 根据设计参数确定IC设计的拥塞的局部区域。 具有特定级别的复杂性的小区在拥塞的局部区域内被识别。 通过向替代单元添加接入点，以与单元相同的逻辑功能在算法上创建替代单元。 然后将该小区替换为局部拥挤区域内的备选小区。

    Improving routability of integrated circuit design without impacting the design area
    2.
    发明授权
    Improving routability of integrated circuit design without impacting the design area 有权
    提高集成电路设计的可布线性，不影响设计区域

    公开(公告)号：US08127263B2

    公开(公告)日：2012-02-28

    申请号：US12364649

    申请日：2009-02-03

    申请人： Pavan Vithal Torvi ,  Girishankar Gurumurthy ,  Dharin N Shah ,  Ajith Harihara Subramonia

    发明人： Pavan Vithal Torvi ,  Girishankar Gurumurthy ,  Dharin N Shah ,  Ajith Harihara Subramonia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.

    摘要翻译： 描述了在不影响该区域的情况下提高集成电路（IC）设计的可布线性。 根据设计参数确定IC设计的拥塞的局部区域。 具有特定级别的复杂性的小区在拥塞的局部区域内被识别。 通过向替代单元添加接入点，以与单元相同的逻辑功能在算法上创建替代单元。 然后将该小区替换为局部拥挤区域内的备选小区。