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1.发明授权Improving routability of integrated circuit design without impacting the design area 有权提高集成电路设计的可布线性，不影响设计区域公开(公告)号：US08127263B2
公开(公告)日：2012-02-28
申请号：US12364649
申请日：2009-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.
摘要翻译： 描述了在不影响该区域的情况下提高集成电路（IC）设计的可布线性。 根据设计参数确定IC设计的拥塞的局部区域。 具有特定级别的复杂性的小区在拥塞的局部区域内被识别。 通过向替代单元添加接入点，以与单元相同的逻辑功能在算法上创建替代单元。 然后将该小区替换为局部拥挤区域内的备选小区。
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公开(公告)号：US20100199252A1
公开(公告)日：2010-08-05
申请号：US12364649
申请日：2009-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Improving the routability of integrated circuit (IC) design without impacting the area. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.
摘要翻译： 提高集成电路（IC）设计的可布线性，而不影响该区域。 根据设计参数确定IC设计的拥塞的局部区域。 具有特定级别的复杂性的小区在拥塞的局部区域内被识别。 通过向替代单元添加接入点，以与单元相同的逻辑功能在算法上创建替代单元。 然后将该小区替换为局部拥挤区域内的备选小区。
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3.发明申请Generation of standard cell library components with increased signal routing resources 有权生成具有增加的信号路由资源的标准单元库组件公开(公告)号：US20090293023A1
公开(公告)日：2009-11-26
申请号：US12124162
申请日：2008-05-21
申请人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
发明人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).
摘要翻译： 生成具有增加信号路由资源的单元。 在一个实施例中，识别和去除源电池的金属层中的电源和接地总线。 终止于已拆卸总线上的任何通孔也可以被去除。 额外的通道和连接被添加到其他所需的层，以提供与由于较早的移除而断开的节点的连接。 根据本发明的一个方面，在芯片设计阶段（即，当将单元实例结合到集成电路中时，这些连接被设计成）被添加。
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4.发明授权Generation of standard cell library components with increased signal routing resources 有权生成具有增加的信号路由资源的标准单元库组件公开(公告)号：US07895551B2
公开(公告)日：2011-02-22
申请号：US12124162
申请日：2008-05-21
申请人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
发明人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).
摘要翻译： 生成具有增加信号路由资源的单元。 在一个实施例中，识别和去除源电池的金属层中的电源和接地总线。 终止于已拆卸总线上的任何通孔也可以被去除。 额外的通道和连接被添加到其他所需的层，以提供与由于较早的移除而断开的节点的连接。 根据本发明的一个方面，在芯片设计阶段（即，当将单元实例结合到集成电路中时，这些连接被设计成）被添加。
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公开(公告)号：US20130173977A1
公开(公告)日：2013-07-04
申请号：US13342030
申请日：2011-12-31
IPC分类号： G01R31/3177 , H03K3/289
CPC分类号： H03K3/35625 , G01R31/318552
摘要： A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.
摘要翻译： 主/从锁存器包括输入级，主锁存器，从锁存器，以及接收异步清零信号。 输入级被布置为响应于时钟信号和门控时钟信号交替地传递或阻塞数据输入信号。 门控时钟信号是当异步清除信号未被置位时的时钟信号的倒数，当异步清除信号被置位时门控时钟信号不活动。 主锁存器以锁存状态接收并锁存通过的数据信号，响应于异步清零信号被断言而清除锁存状态，并产生主锁存输出信号。 从锁存器在锁存状态下接收并锁存主锁存器输出信号。 响应于异步清除信号被断言，清除的锁存状态被传递到从锁存器。
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公开(公告)号：US08578224B2
公开(公告)日：2013-11-05
申请号：US13342030
申请日：2011-12-31
IPC分类号： G01R31/28
CPC分类号： H03K3/35625 , G01R31/318552
摘要： A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.
摘要翻译： 主/从锁存器包括输入级，主锁存器，从锁存器，以及接收异步清零信号。 输入级被布置为响应于时钟信号和门控时钟信号交替地传递或阻塞数据输入信号。 门控时钟信号是当异步清除信号未被置位时的时钟信号的倒数，当异步清除信号被置位时门控时钟信号不活动。 主锁存器以锁存状态接收并锁存通过的数据信号，响应于异步清零信号被断言而清除锁存状态，并产生主锁存输出信号。 从锁存器在锁存状态下接收并锁存主锁存器输出信号。 响应于异步清除信号被断言，清除的锁存状态被传递到从锁存器。
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公开(公告)号：US08112737B2
公开(公告)日：2012-02-07
申请号：US12233784
申请日：2008-09-19
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.
摘要翻译： 一种方法生成集成电路的设计布局。 为集成电路提供了一种设计。 库细胞根据设计选择。 库单元被映射到芯片区域图。 未照射的电池填充有填充电池。 选择文库细胞的临界细胞。 所选择的临界电池相对于接触电阻和/或接触电容而改变。 提供包含改变的单元格的地图作为设计布局。
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8.发明授权Representing data having multi-dimensional input vectors and corresponding output element by piece-wise polynomials 有权通过分段多项式表示具有多维输入向量的数据和相应的输出元素公开(公告)号：US07483819B2
公开(公告)日：2009-01-27
申请号：US10904973
申请日：2004-12-07
申请人： Girishankar Gurumurthy , Shitanshu Krishnachandra Tiwari , Hugh Thomas Mair , Sumanth K Gururajarao
发明人： Girishankar Gurumurthy , Shitanshu Krishnachandra Tiwari , Hugh Thomas Mair , Sumanth K Gururajarao
IPC分类号： G06F17/10
CPC分类号： G06F17/175
摘要： Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial is a data set cannot be entirely modeled by one polynomial. Another aspect of the present invention reduces the number of combinations (of orders for sub-polynomials forming the polynomials) to be tried in determining polynomials, meeting various accuracy requirements. Such a reduction is obtained based on a recognition that when the order in one dimension alone is increased and the result does not lead to acceptable accuracy of the polynomial, the combinations with a lesser number for the order (of the dimension) can be ruled out.
摘要翻译： 确定分段多项式，它们一起代表具有多维输入向量和相应输出元素的大数据集。 在一个实施例中，函数/过程/例程被递归地调用/调用以确定分段多项式是数据集不能被一个多项式完全建模。 本发明的另一方面减少了在确定多项式时要尝试的满足各种精度要求的组合（形成多项式的子多项式的顺序）的数量。 基于这样的认识可以获得这样的减少：当一维中的顺序增加并且结果不会导致多项式的可接受的精度时，可以排除具有较小数量（对于维度）的组合， 。
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公开(公告)号：US20090013297A1
公开(公告)日：2009-01-08
申请号：US12233784
申请日：2008-09-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.
摘要翻译： 一种方法生成集成电路的设计布局。 为集成电路提供了一种设计。 库细胞根据设计选择。 库单元被映射到芯片区域图。 未照射的电池填充有填充电池。 选择文库细胞的临界细胞。 所选择的临界电池相对于接触电阻和/或接触电容而改变。 提供包含改变的单元格的地图作为设计布局。
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公开(公告)号：US20070290270A1
公开(公告)日：2007-12-20
申请号：US11745250
申请日：2007-05-07
申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
发明人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
IPC分类号： H01L29/768 , G06F17/50
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11807
摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要翻译： 集成电路。 集成电路包括具有排列成行的布局的区域。 每行可由一对行边界定义。 集成电路还包括多个单元，包括第一组单元。 第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管 。
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