公开(公告)号：US07602799B2

公开(公告)日：2009-10-13

申请号：US11476630

申请日：2006-06-29

申请人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

发明人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

IPC分类号： H04L12/54

CPC分类号： H04L41/0896 ,  H04L12/12 ,  Y02D50/30 ,  Y02D50/40

摘要： A network management apparatus interconnects a plurality of computers through physical lines having a predetermined line speed to manage a switch apparatus constructing a parallel computer system. The switch apparatus comprises a plurality of physical port units to enable or disable the same through individual power supply ON/OFF control for the physical port units, thereby changing and controlling the line transmission speed according to the enable number. A logical port constructing unit in the network management apparatus bundles the physical lines by a plurality of physical port units in the switch apparatus to construct logical lines. A port control unit changes the number of operations of a plurality of physical port units assigned to the logical port units through the power supply ON/OFF control according to a necessary data transmission speed for the logical port units, thereby dynamically changing the line transmission speed.

摘要翻译： 网络管理装置通过具有预定线路速度的物理线路互连多台计算机，以管理构建并行计算机系统的交换装置。 开关装置包括多个物理端口单元，以通过用于物理端口单元的单独电源ON / OFF控制来实现或禁用相同的，从而根据启用号码来改变和控制线路传输速度。 网络管理装置中的逻辑端口构成单元通过开关装置中的多个物理端口单元对物理线路进行捆绑，构成逻辑线路。 端口控制单元根据逻辑端口单元的必要数据传输速度，通过电源ON / OFF控制来改变分配给逻辑端口单元的多个物理端口单元的操作次数，从而动态地改变线路传输速度 。

公开(公告)号：US20070211628A1

公开(公告)日：2007-09-13

申请号：US11476630

申请日：2006-06-29

申请人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

发明人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

IPC分类号： H04L12/26

CPC分类号： H04L41/0896 ,  H04L12/12 ,  Y02D50/30 ,  Y02D50/40

摘要： A network management apparatus interconnects a plurality of computers through physical lines having a predetermined line speed to manage a switch apparatus constructing a parallel computer system. The switch apparatus comprises a plurality of physical port units to enable or disable the same through individual power supply ON/OFF control for the physical port units, thereby changing and controlling the line transmission speed according to the enable number. A logical port constructing unit in the network management apparatus bundles the physical lines by a plurality of physical port units in the switch apparatus to construct logical lines. A port control unit changes the number of operations of a plurality of physical port units assigned to the logical port units through the power supply ON/OFF control according to a necessary data transmission speed for the logical port units, thereby dynamically changing the line transmission speed.

摘要翻译： 网络管理装置通过具有预定线路速度的物理线路互连多台计算机，以管理构建并行计算机系统的交换装置。 开关装置包括多个物理端口单元，以通过用于物理端口单元的单独电源ON / OFF控制来实现或禁用相同的，从而根据启用号码来改变和控制线路传输速度。 网络管理装置中的逻辑端口构成单元通过开关装置中的多个物理端口单元对物理线路进行捆绑，构成逻辑线路。 端口控制单元根据逻辑端口单元的必要数据传输速度，通过电源ON / OFF控制来改变分配给逻辑端口单元的多个物理端口单元的操作次数，从而动态地改变线路传输速度 。

公开(公告)号：US20070214248A1

公开(公告)日：2007-09-13

申请号：US11476650

申请日：2006-06-29

申请人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

发明人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

IPC分类号： G06F15/173

CPC分类号： H04L12/66 ,  H04L41/0896 ,  H04L43/0894

摘要： An interconnection network is provided with switch devices for computers for a plurality of computers, respectively, a predetermined number of physical lines for switch devices for computers are bound to form each of logical lines, the physical lines forming the logical lines interconnect the other switch devices for computer via a plurality of switch devices for relay to form a parallel computer system. When a data transmission speed required between the computers is judged to be lower than a line transmission speed determined by the number of physical lines of any switch device for relay, switch setting-off unit turns off power of the whole switch device for relay that has been judged to shut off the switch device for relay from the interconnection network.

摘要翻译： 互连网络分别设置有用于多个计算机的计算机的交换设备，用于计算机的交换设备的预定数量的物理线路将形成每个逻辑线路，形成逻辑线路的物理线路将其他交换机设备 用于通过多个用于继电器的开关装置的计算机以形成并行计算机系统。 当计算机之间所需的数据传输速度被判定为低于由任何用于继电器的开关装置的物理线路数确定的线路传输速度时，开关设置单元关闭具有 被判断为从互连网络切断用于中继的交换设备。

公开(公告)号：US07653738B2

公开(公告)日：2010-01-26

申请号：US11476650

申请日：2006-06-29

申请人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

发明人： Yoshiro Ikeda ,  Akihiro Yasuo ,  Atsushi Mori ,  Akira Asato ,  Katsuhiko Nishikawa

IPC分类号： G06F15/16

CPC分类号： H04L12/66 ,  H04L41/0896 ,  H04L43/0894

摘要： An interconnection network is provided with switch devices for computers for a plurality of computers, respectively, a predetermined number of physical lines for switch devices for computers are bound to form each of logical lines, the physical lines forming the logical lines interconnect the other switch devices for computer via a plurality of switch devices for relay to form a parallel computer system. When a data transmission speed required between the computers is judged to be lower than a line transmission speed determined by the number of physical lines of any switch device for relay, switch setting-off unit turns off power of the whole switch device for relay that has been judged to shut off the switch device for relay from the interconnection network.

摘要翻译： 互连网络分别设置有用于多个计算机的计算机的交换设备，用于计算机的交换设备的预定数量的物理线路将形成每个逻辑线路，形成逻辑线路的物理线路将其他交换机设备 用于经由用于继电器的多个开关装置的计算机以形成并行计算机系统。 当计算机之间所需的数据传输速度被判定为低于由用于继电器的任何开关装置的物理线数确定的线路传输速度时，开关断开单元关闭具有 被判断为从互连网络切断用于中继的交换设备。

公开(公告)号：US06195741B1

公开(公告)日：2001-02-27

申请号：US09145034

申请日：1998-09-01

申请人： Akira Asato

发明人： Akira Asato

IPC分类号： G06F930

CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087

摘要： A data processing system which is able to execute, decode and encode process variable length code (VLC) data in a finite number of programming steps and thereby reduce the time required to manipulate VLC data. This is accomplished by using buffer registers to store VLC data loaded from memory and VLC data to be stored to memory. Offset registers are used to indicate the size of the blank region within the buffer registers provided. Using these offset registers load and store processing between the memory and buffer registers and shift processing within the buffer registers can easily be accomplished.

摘要翻译： 一种数据处理系统，其能够在有限数量的编程步骤中执行，解码和编码过程可变长度代码（VLC）数据，从而减少操纵VLC数据所需的时间。 这是通过使用缓冲寄存器来存储从存储器加载的VLC数据并将VLC数据存储到存储器来实现的。 偏移寄存器用于指示所提供的缓冲寄存器中空白区域的大小。 使用这些偏移寄存器在存储器和缓冲寄存器之间加载和存储处理，并且可以容易地实现缓冲寄存器内的移位处理。

公开(公告)号：US06275921B1

公开(公告)日：2001-08-14

申请号：US09045117

申请日：1998-03-20

申请人： Yasushi Iwata ,  Akira Asato

发明人： Yasushi Iwata ,  Akira Asato

IPC分类号： G06F1576

CPC分类号： G06F9/3853

摘要： A data processing device includes an instruction storage memory which stores load instructions by eliminating NOP instructions for insertion into a load module of a VLIW computer. The data processing device also includes a device to expand the compressed load module automatically by a hardware circuit during instruction execution. The data processing device compresses and stores specific instruction code strings in memory with information indicating a form of compression and then restores the instruction code strings to an original format when read from memory according to the compression information. Information indicating an original storage position is attached to each instruction code, instruction code strings are stored in memory without specific instruction codes, and then restored to the original code strings when read from memory according to the storage position information.

摘要翻译： 数据处理装置包括指令存储器，其通过消除用于插入到VLIW计算机的加载模块中的NOP指令来存储加载指令。 数据处理装置还包括在指令执行期间由硬件电路自动扩展压缩负载模块的装置。 数据处理装置利用指示压缩形式的信息将特定指令代码串压缩存储在存储器中，然后根据压缩信息从存储器读取时将指令代码串恢复为原始格式。 指示原始存储位置的信息附加到每个指令代码，指令代码串被存储在没有特定指令代码的存储器中，然后根据存储位置信息从存储器读取时恢复到原始代码串。

公开(公告)号：US06145074A

公开(公告)日：2000-11-07

申请号：US044846

申请日：1998-03-20

申请人： Akira Asato

发明人： Akira Asato

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859

摘要： A data processing device having a pipeline bypass function passes an operation result of a preceding instruction to a succeeding instruction as a source operand before writing the operation result to a register. A source operand bypass specification field and a source operand register field in the instruction code are provided to control passing of the operation result. A source operand selector responds to the source operand bypass specification field by selecting data either from the register or the bypasses as a pipeline input data.

摘要翻译： 具有流水线旁路功能的数据处理装置在将操作结果写入寄存器之前，将前一指令的操作结果作为源操作数传递给后续指令。 指令代码中的源操作数旁路指定字段和源操作数寄存器字段用于控制操作结果的传递。 源操作数选择器通过从寄存器或旁路中选择数据作为流水线输入数据来响应源操作数旁路指定字段。

公开(公告)号：US6038396A

公开(公告)日：2000-03-14

申请号：US42799

申请日：1998-03-17

申请人： Yasushi Iwata ,  Akira Asato

发明人： Yasushi Iwata ,  Akira Asato

IPC分类号： G06F9/38 ,  G06F9/45

CPC分类号： G06F8/445 ,  G06F8/447

摘要： A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each slot of the VLIW instruction, is divided corresponding to each slot and stored into a plurality of intermediate code files. The instructions of the intermediate code format stored in the intermediate code files are then read in serially to execute an instruction scheduling process, taking into account dependency between instructions. The serialized instructions of the intermediate code format are converted into parallel assembly code, and an object program of the parallel assembly code is output.

摘要翻译： 使用编译装置和方法以及记录介质来促进VLIW计算机系统的汇编代码编程。 针对VLIW指令的每个时隙指定的中间代码格式的指令根据每个时隙划分并被存储到多个中间代码文件中。 然后，存储在中间代码文件中的中间代码格式的指令被顺序读取以执行指令调度处理，同时考虑指令之间的依赖关系。 将中间代码格式的序列化指令转换为并行汇编代码，并输出并行汇编代码的对象程序。