公开(公告)号：US07994824B2

公开(公告)日：2011-08-09

申请号：US12742572

申请日：2008-11-14

申请人： Fabio Alessio Marino ,  Alessandro Paccagnella

发明人： Fabio Alessio Marino ,  Alessandro Paccagnella

IPC分类号： H03K19/094 ,  H03K19/20

CPC分类号： G06F7/5016 ,  H03K19/0963

摘要： Logic Gate (100), particularly for integrated circuits including a Boolean network (105) having at least an input (106) and having at least an output node (107) and at least a terminal (108) connected to a first node at fixed potential (109) corresponding to a first logical level of the gate. The gate is characterized by the fact that the output node (107) is connected to a first pair of switches including a first switch (101) and a second switch (102), which are activated alternately, and are connected respectively, by a respective terminal, to the first node (109) at fixed potential and to the output node (107). Between the two switches there is a second pair of switches (103, 104) connected to a second node at fixed potential (110) corresponding to a second logical level of the gate. The switches of the second pair of switches are connected together in a way that the turning on of one switch of the second pair involves the turning off of the other switch of the second pair and the turning on of one of the switches of the second pair is suitable to bring the output node (107) to the potential of the second node at fixed potential (110).

摘要翻译： 逻辑门（100），特别是对于包括至少具有输入（106）并且至少具有输出节点（107）的至少一个终端（108）的布尔网络（105）的集成电路，所述终端连接到固定的第一节点 电位（109）对应于门的第一逻辑电平。 门的特征在于，输出节点（107）连接到包括第一开关（101）和第二开关（102）的第一对开关，其交替地被激活，并且分别由相应的 终端，到固定电位的第一节点（109）和输出节点（107）。 在两个开关之间存在第二对开关（103,104），其连接到对应于门的第二逻辑电平的固定电位（110）的第二节点。 第二对开关的开关以这样的方式连接在一起，使得第二对开关的一个开关的接通涉及第二对的另一开关的断开以及第二对开关中的一个开关的导通 适于将输出节点（107）带到固定电位（110）处的第二节点的电位。

公开(公告)号：US20100259301A1

公开(公告)日：2010-10-14

申请号：US12742572

申请日：2008-11-14

申请人： Fabio Alessio Marino ,  Alessandro Paccagnella

发明人： Fabio Alessio Marino ,  Alessandro Paccagnella

IPC分类号： H03K19/094

CPC分类号： G06F7/5016 ,  H03K19/0963

摘要： Logic Gate (100), particularly for integrated circuits including a Boolean network (105) having at least an input (106) and having at least an output node (107) and at least a terminal (108) connected to a first node at fixed potential (109) corresponding to a first logical level of the gate. The gate is characterized by the fact that the output node (107) is connected to a first pair of switches including a first switch (101) and a second switch (102), which are activated alternately, and are connected respectively, by a respective terminal, to the first node (109) at fixed potential and to the output node (107). Between the two switches there is a second pair of switches (103, 104) connected to a second node at fixed potential (110) corresponding to a second logical level of the gate. The switches of the second pair of switches are connected together in a way that the turning on of one switch of the second pair involves the turning off of the other switch of the second pair and the turning on of one of the switches of the second pair is suitable to bring the output node (107) to the potential of the second node at fixed potential (110).

摘要翻译： 逻辑门（100），特别是对于包括至少具有输入（106）并且至少具有输出节点（107）的至少一个终端（108）的布尔网络（105）的集成电路，所述终端连接到固定的第一节点 电位（109）对应于门的第一逻辑电平。 门的特征在于，输出节点（107）连接到包括第一开关（101）和第二开关（102）的第一对开关，其交替地被激活，并且分别由相应的 终端，到固定电位的第一节点（109）和输出节点（107）。 在两个开关之间存在第二对开关（103,104），其连接到对应于门的第二逻辑电平的固定电位（110）的第二节点。 第二对开关的开关以这样的方式连接在一起，使得第二对开关的一个开关的接通涉及第二对的另一个开关的断开以及第二对开关中的一个开关的导通 适于将输出节点（107）带到固定电位（110）处的第二节点的电位。

公开(公告)号：US20100140488A1

公开(公告)日：2010-06-10

申请号：US12329740

申请日：2008-12-08

申请人： Angelo Visconti ,  Mauro Bonanomi ,  Giorgio Cellere ,  Alessandro Paccagnella

发明人： Angelo Visconti ,  Mauro Bonanomi ,  Giorgio Cellere ,  Alessandro Paccagnella

IPC分类号： G01T1/02

CPC分类号： G01T1/026 ,  G01T1/00 ,  H01L31/115 ,  H04N5/357

摘要： A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution.

摘要翻译： 存储器单元的二维阵列可以用于实现空间剂量计。 单元的二维阵列可以由集成电路存储器实现由于集成电路存储器的尺寸相对较小，所得阵列的分辨率可能小于100纳米。 作为辐射暴露的结果，每个细胞的阈值电压的变化可用于计算在每个细胞处观察到的剂量，允许二维尺度下的亚微米分辨率的剂量分布。

公开(公告)号：US08791418B2

公开(公告)日：2014-07-29

申请号：US12329740

申请日：2008-12-08

申请人： Angelo Visconti ,  Mauro Bonanomi ,  Giorgio Cellere ,  Alessandro Paccagnella

发明人： Angelo Visconti ,  Mauro Bonanomi ,  Giorgio Cellere ,  Alessandro Paccagnella

IPC分类号： G01T1/02 ,  H04N5/357 ,  H01L31/115

CPC分类号： G01T1/026 ,  G01T1/00 ,  H01L31/115 ,  H04N5/357

摘要： A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory. Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution.

摘要翻译： 存储器单元的二维阵列可以用于实现空间剂量计。 单元的二维阵列可以由集成电路存储器来实现。 由于集成电路存储器的尺寸相对较小，所得阵列的分辨率可能小于100纳米。 作为辐射暴露的结果，每个细胞的阈值电压的变化可用于计算在每个细胞处观察到的剂量，允许二维尺度下的亚微米分辨率的剂量分布。