公开(公告)号：US20090113256A1

公开(公告)日：2009-04-30

申请号：US11977686

申请日：2007-10-24

Applicant: Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

Inventor： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

IPC: G06K5/04

CPC classification number: H03M13/116 ,  H03M13/1114 ,  H03M13/112 ,  H03M13/1128 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1185 ,  H03M13/6566

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Decoding is performed in a pipelined manner using a layered belief propagation technique and scalable resources, which are configurable to accommodate at least two codeword lengths and at least two code rates. A computer program product, apparatus and device are also described.

Abstract translation: 本发明涉及低密度奇偶校验解码。 描述用于解码编码数据块的方法。 使用分层置信传播技术和可缩放资源以流水线方式执行解码，其可配置为容纳至少两个码字长度和至少两个码率。 还描述了计算机程序产品，装置和装置。

公开(公告)号：US20080052608A1

公开(公告)日：2008-02-28

申请号：US11498272

申请日：2006-08-03

Applicant: Arnab Chakrabarti ,  Alexandre de Baynast ,  Ashutosh Sabharwal ,  Behnaam Aazhang

Inventor： Arnab Chakrabarti ,  Alexandre de Baynast ,  Ashutosh Sabharwal ,  Behnaam Aazhang

IPC: G06F11/08

CPC classification number: H04L1/0045 ,  H04B7/155 ,  H04B7/2606 ,  H04L2001/0097

Abstract: A method including transmitting a binary vector from a source node to a relay node and receiving a signal vector at the relay node. The method also includes compressing the signal at the relay node by multiplying the signal with a matrix using probabilities and converting output probabilities from the multiplying into retransmission signal amplitudes, the signal amplitude depending not only on a probability of a bit but on a transmission power constraint at the relay node. The method also includes transmitting, by the relay node, estimates of information from the source node to a destination node.

Abstract translation: 一种方法，包括从源节点向中继节点发送二进制向量并在中继节点处接收信号向量。 该方法还包括通过使用概率将信号与矩阵相乘来压缩中继节点处的信号，并将输出概率从乘法转换为重发信号幅度，信号幅度不仅取决于比特的概率，而且取决于发射功率约束 在中继节点。 该方法还包括由中继节点发送从源节点到目的地节点的信息估计。

公开(公告)号：US08219876B2

公开(公告)日：2012-07-10

申请号：US11977644

申请日：2007-10-24

Applicant: Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

Inventor： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

IPC: H03M13/00 ,  G11C29/00

CPC classification number: H03M13/1148 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/6566

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Abstract translation: 本发明涉及低密度奇偶校验解码。 描述用于解码编码数据块的方法。 存储包括数据子块的编码数据块。 使用不规则的块结构的奇偶校验矩阵以流水线方式执行解码，其中奇偶校验矩阵的至少两个数据子块矩阵从多个时钟周期中的每一个读出并写入。 数据子块的读取和写入被均匀分布在存储器的至少两个区域之间。 以等于或低于预定阈值长度的周期的移位值执行解码。 还描述了一种装置，计算机程序产品和装置。

公开(公告)号：US20090113276A1

公开(公告)日：2009-04-30

申请号：US11977644

申请日：2007-10-24

Applicant: Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

Inventor： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

IPC: H03M13/00

CPC classification number: H03M13/1148 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/6566

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Abstract translation: 本发明涉及低密度奇偶校验解码。 描述用于解码编码数据块的方法。 存储包括数据子块的编码数据块。 使用不规则的块结构的奇偶校验矩阵以流水线方式执行解码，其中奇偶校验矩阵的至少两个数据子块矩阵从多个时钟周期中的每一个读出并写入。 数据子块的读取和写入被均匀分布在存储器的至少两个区域之间。 以等于或低于预定阈值长度的周期的移位值执行解码。 还描述了一种装置，计算机程序产品和装置。

公开(公告)号：US20120278811A1

公开(公告)日：2012-11-01

申请号：US13093846

申请日：2011-04-26

Applicant: Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler ,  Thomas Santen ,  Satnam Singh ,  Alain Gefflaut ,  William Dunlap

Inventor： Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler ,  Thomas Santen ,  Satnam Singh ,  Alain Gefflaut ,  William Dunlap

IPC: G06F9/46

CPC classification number: G06F9/5027 ,  G06F2209/501 ,  Y02D10/22

Abstract: A stream processing execution engine evaluates development-time performance characteristic estimates in combination with run-time parameters to schedule execution of stream processing software components in a stack of a stream processing application that satisfy a defined performance criterion in a heterogeneous hardware device. A stream processing application includes a stack of interdependent stream processing software components. A stream processing execution engine evaluates one or more performance characteristics of multiple computational resources in the heterogeneous hardware device. Each performance characteristic is associated with performance of a computational resource in executing a computational-resource-dependent instance of a stream processing software component. The stream processing execution engine schedules within the run-time environment a computational resource on which to execute a computational-resource-dependent instance of one of the stream processing software components. The computational-resource-dependent instance is targeted for execution on the computational resource that satisfies a performance policy attributed to the stream processing software component.

Abstract translation: 流处理执行引擎结合运行时参数评估开发时性能特性估计，以调度在异构硬件设备中满足定义的性能标准的流处理应用的堆栈中的流处理软件组件的执行。 流处理应用包括一组相互依赖的流处理软件组件。 流处理执行引擎评估异构硬件设备中的多个计算资源的一个或多个性能特征。 每个性能特征与执行流处理软件组件的依赖于计算资源的实例相关联的计算资源的性能。 流处理执行引擎在运行时环境内调度计算资源，在其上执行流处理软件组件之一的基于计算资源的依赖实例。 计算资源依赖实例被定位为在满足流处理软件组件的性能策略的计算资源上执行。

公开(公告)号：US20120240003A1

公开(公告)日：2012-09-20

申请号：US13479745

申请日：2012-05-24

Applicant: Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

Inventor： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

IPC: H03M13/11 ,  G06F11/10

CPC classification number: H03M13/1148 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/6566

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Abstract translation: 本发明涉及低密度奇偶校验解码。 描述用于解码编码数据块的方法。 存储包括数据子块的编码数据块。 使用不规则的块结构的奇偶校验矩阵以流水线方式执行解码，其中奇偶校验矩阵的至少两个数据子块矩阵从多个时钟周期中的每一个读出并写入。 数据子块的读取和写入被均匀分布在存储器的至少两个区域之间。 以等于或低于预定阈值长度的周期的移位值执行解码。 还描述了一种装置，计算机程序产品和装置。

公开(公告)号：US07961726B2

公开(公告)日：2011-06-14

申请号：US12246683

申请日：2008-10-07

Applicant: Zhou Wang ,  Alain Gefflaut ,  Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler

Inventor： Zhou Wang ,  Alain Gefflaut ,  Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler

IPC: H04L12/28

CPC classification number: H04L69/08 ,  H04L69/24

Abstract: A framework capable of providing transparent handling of network traffic in close proximity networks such as home networks is provided. A single virtual network interface is exposed to users/applications on connected devices. A virtual network interface manager determines available physical network interfaces and switches to a different physical network interface or a different configuration on the same physical network interface in a transparent manner to the communicating application(s). This enables the framework to optimize network communications for the communicating applications, devices, and users based on predefined criteria, application requirements such as different data throughput, or changing environment conditions such as interference. Network communication operations are also simplified for users since they are no longer required to have the necessary knowledge for configuring physical network interfaces manually in response to changing conditions.

Abstract translation: 提供了能够提供诸如家庭网络之类的近距离网络中的网络流量的透明处理的框架。 单个虚拟网络接口暴露给连接设备上的用户/应用程序。 虚拟网络接口管理器以透明的方式确定可用的物理网络接口，并以相同的物理网络接口切换到不同的物理网络接口或不同的配置。 这使得框架能够基于预定义的标准，诸如不同数据吞吐量的应用需求或改变环境条件（例如干扰）来优化用于通信应用，设备和用户的网络通信。 网络通信操作也为用户简化，因为不再需要具备为响应不断变化的条件手动配置物理网络接口的必要知识。

公开(公告)号：US20100085975A1

公开(公告)日：2010-04-08

申请号：US12246683

申请日：2008-10-07

Applicant: Zhou Wang ,  Alain Gefflaut ,  Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler

Inventor： Zhou Wang ,  Alain Gefflaut ,  Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler

IPC: H04L12/28

CPC classification number: H04L69/08 ,  H04L69/24

Abstract: A framework capable of providing transparent handling of network traffic in close proximity networks such as home networks is provided. A single virtual network interface is exposed to users/applications on connected devices. A virtual network interface manager determines available physical network interfaces and switches to a different physical network interface or a different configuration on the same physical network interface in a transparent manner to the communicating application(s). This enables the framework to optimize network communications for the communicating applications, devices, and users based on predefined criteria, application requirements such as different data throughput, or changing environment conditions such as interference. Network communication operations are also simplified for users since they are no longer required to have the necessary knowledge for configuring physical network interfaces manually in response to changing conditions.

Abstract translation: 提供了能够提供诸如家庭网络之类的近距离网络中的网络流量的透明处理的框架。 单个虚拟网络接口暴露给连接设备上的用户/应用程序。 虚拟网络接口管理器以透明的方式确定可用的物理网络接口，并以相同的物理网络接口切换到不同的物理网络接口或不同的配置。 这使得框架能够基于预定义的标准，诸如不同数据吞吐量的应用需求或改变环境条件（例如干扰）来优化用于通信应用，设备和用户的网络通信。 网络通信操作也为用户简化，因为不再需要具备为响应不断变化的条件手动配置物理网络接口的必要知识。

公开(公告)号：US08869162B2

公开(公告)日：2014-10-21

申请号：US13093846

申请日：2011-04-26

Applicant: Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler ,  Thomas Santen ,  Satnam Singh ,  Alain Gefflaut ,  William Dunlap

Inventor： Alexandre de Baynast ,  Arsalan Ahmad ,  Andreas Steinmetzler ,  Thomas Santen ,  Satnam Singh ,  Alain Gefflaut ,  William Dunlap

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5027 ,  G06F2209/501 ,  Y02D10/22

Abstract: A stream processing execution engine evaluates development-time performance characteristic estimates in combination with run-time parameters to schedule execution of stream processing software components in a stack of a stream processing application that satisfy a defined performance criterion in a heterogeneous hardware device. A stream processing application includes a stack of interdependent stream processing software components. A stream processing execution engine evaluates one or more performance characteristics of multiple computational resources in the heterogeneous hardware device. Each performance characteristic is associated with performance of a computational resource in executing a computational-resource-dependent instance of a stream processing software component. The stream processing execution engine schedules within the run-time environment a computational resource on which to execute a computational-resource-dependent instance of one of the stream processing software components. The computational-resource-dependent instance is targeted for execution on the computational resource that satisfies a performance policy attributed to the stream processing software component.

Abstract translation: 流处理执行引擎结合运行时参数评估开发时性能特性估计，以调度在异构硬件设备中满足定义的性能标准的流处理应用的堆栈中的流处理软件组件的执行。 流处理应用包括一组相互依赖的流处理软件组件。 流处理执行引擎评估异构硬件设备中的多个计算资源的一个或多个性能特征。 每个性能特征与执行流处理软件组件的依赖于计算资源的实例相关联的计算资源的性能。 流处理执行引擎在运行时环境内调度计算资源，在其上执行流处理软件组件之一的基于计算资源的依赖实例。 计算资源依赖实例被定位为在满足流处理软件组件的性能策略的计算资源上执行。

公开(公告)号：US08869003B2

公开(公告)日：2014-10-21

申请号：US13479745

申请日：2012-05-24

Applicant: Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

Inventor： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

IPC: H03M13/00 ,  G11C29/00 ,  H03M13/11

CPC classification number: H03M13/1148 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/6566

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Abstract translation: 本发明涉及低密度奇偶校验解码。 描述用于解码编码数据块的方法。 存储包括数据子块的编码数据块。 使用不规则的块结构的奇偶校验矩阵以流水线方式执行解码，其中奇偶校验矩阵的至少两个数据子块矩阵从多个时钟周期中的每一个读出并写入。 数据子块的读取和写入被均匀分布在存储器的至少两个区域之间。 以等于或低于预定阈值长度的周期的移位值执行解码。 还描述了一种装置，计算机程序产品和装置。