Method and apparatus for packet switching
    1.
    发明授权
    Method and apparatus for packet switching 有权
    分组交换的方法和装置

    公开(公告)号:US08874876B2

    公开(公告)日:2014-10-28

    申请号:US13323594

    申请日:2011-12-12

    CPC分类号: H04L49/3009 H04L49/356

    摘要: A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules.

    摘要翻译: 提供了一种用于执行分组查找的方法。 数据包(每个都有一个主体和一个头)被接收并解析为解析头。 将哈希函数应用于每个头部,并且将每个散列头部与存储在主表中的多个二进制规则进行比较,其中每个二进制规则是来自第一组三元规则的至少一个三元规则的二进制版本。 对于与多个规则的每个匹配失败,使用与每个匹配失败相关联的标题来搜索次表,其中次表包括第二组三进制规则。

    Multiport memory emulation using single-port memory devices
    2.
    发明授权
    Multiport memory emulation using single-port memory devices 有权
    使用单端口存储设备的多端口存储器仿真

    公开(公告)号:US09158683B2

    公开(公告)日:2015-10-13

    申请号:US13571343

    申请日:2012-08-09

    IPC分类号: G06F12/06 G11C8/16

    CPC分类号: G06F12/06 G11C8/16 Y02D10/13

    摘要: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

    摘要翻译: 多端口存储器仿真器在一个操作时钟周期中接收用于并行处理存储器命令的第一和第二存储器命令。 数据操作数存储在排列为行和存储体的位单元的存储器阵列中。 辅助存储体提供用于物理存储每行的附加字的比特单元。 第一和第二存储器命令中的每一个的存储体地址部分分别被转换为第一和第二物理存储体地址。 响应于银行地址部分相等的确定并且与第一银行地址相关联的银行被指定为用于随后接收的存储器命令的当前未使用的存储体,第二物理存储体地址被分配当前未使用的存储体的存储体地址 响应于银行地址部分相等的确定。 可以同时进行读写操作。

    MULTIPORT MEMORY EMULATION USING SINGLE-PORT MEMORY DEVICES
    3.
    发明申请
    MULTIPORT MEMORY EMULATION USING SINGLE-PORT MEMORY DEVICES 有权
    使用单端口存储器件进行多重存储器仿真

    公开(公告)号:US20140047197A1

    公开(公告)日:2014-02-13

    申请号:US13571343

    申请日:2012-08-09

    IPC分类号: G06F12/00

    CPC分类号: G06F12/06 G11C8/16 Y02D10/13

    摘要: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

    摘要翻译: 多端口存储器仿真器在一个操作时钟周期中接收用于并行处理存储器命令的第一和第二存储器命令。 数据操作数存储在排列为行和存储体的位单元的存储器阵列中。 辅助存储体提供用于物理存储每行的附加字的比特单元。 第一和第二存储器命令中的每一个的存储体地址部分分别被转换为第一和第二物理存储体地址。 响应于银行地址部分相等的确定并且与第一银行地址相关联的银行被指定为用于随后接收的存储器命令的当前未使用的存储体,第二物理存储体地址被分配当前未使用的存储体的存储体地址 响应于银行地址部分相等的确定。 可以同时进行读写操作。

    METHOD AND APPARATUS FOR PACKET SWITICHING
    4.
    发明申请
    METHOD AND APPARATUS FOR PACKET SWITICHING 有权
    用于分组交换的方法和装置

    公开(公告)号:US20120246400A1

    公开(公告)日:2012-09-27

    申请号:US13323594

    申请日:2011-12-12

    IPC分类号: G06F12/00

    CPC分类号: H04L49/3009 H04L49/356

    摘要: A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules.

    摘要翻译: 提供了一种用于执行分组查找的方法。 数据包(每个都有一个主体和一个头)被接收并解析为解析头。 将哈希函数应用于每个头部,并且将每个散列头部与存储在主表中的多个二进制规则进行比较,其中每个二进制规则是来自第一组三元规则的至少一个三元规则的二进制版本。 对于与多个规则的每个匹配失败,使用与每个匹配失败相关联的标题来搜索次表,其中次表包括第二组三进制规则。