Method and apparatus for improved throughput in a multi-node
communication system with a shared resource
    2.
    发明授权
    Method and apparatus for improved throughput in a multi-node communication system with a shared resource 失效
    用于在具有共享资源的多节点通信系统中提高吞吐量的方法和装置

    公开(公告)号:US5467352A

    公开(公告)日:1995-11-14

    申请号:US192884

    申请日:1994-02-07

    CPC分类号: H04L12/433

    摘要: A non-quota access indicator is circulated among nodes in a multi-node quota based communication system with a shared resource, indicating maximum possible non-quota access to the shared resource to a given node receiving same. Upon arrival at a node, the indicator is saved and then updated to reflect the current status of that node as either starved or satisfied, the former being a condition of currently having quota remaining and a shared resource access requirement, and the latter being a condition of either currently having no remaining quota or having no current shared resource access requirement. After updating, the node immediately propagates the indicator to the next node in the system. When a node without quota requires access to the shared resource, it compares its requirement to the last stored indicator and accesses the shared resource if the stored indicator is equal to or greater than the access requirement.

    摘要翻译: 非配额访问指示符在具有共享资源的基于多节点配额的通信系统中的节点之间传播,指示对给予接收到该节点的给定节点的共享资源的最大可能非配额访问。 在到达节点时,指示符被保存并且被更新以反映该节点的当前状态为饥饿或满足,前者是当前具有剩余配额的条件和共享资源访问要求,后者是条件 目前没有剩余配额或没有当前的共享资源访问要求。 更新后,节点立即将指示符传播到系统中的下一个节点。 当没有配额的节点需要访问共享资源时,如果存储的指示符等于或大于访问要求,则将其要求与最后存储的指示符进行比较,并访问共享资源。

    Loadable ripple counter
    4.
    发明授权
    Loadable ripple counter 失效
    可加载纹波计数器

    公开(公告)号:US4891827A

    公开(公告)日:1990-01-02

    申请号:US164584

    申请日:1988-03-07

    申请人: Andrew E. Slater

    发明人: Andrew E. Slater

    IPC分类号: H03K23/58 H03K23/66

    CPC分类号: H03K23/58 H03K23/665

    摘要: A loadable N-bit ripple counter having N bit subcircuits that each inlude a flip-flop and a bit loading element. The flip-flop output is controllable to a known state when a flip-flop control signal is asserted. The bit loading element is connected to receive the flip-flop output and a bit input of a multibit number being loaded and to provide a bit output of the counter, the bit output being controlled by the states of the flip-flop output and the bit input, and, except for the most significant bit, serving as a clock for the next more significant bit subcircuit.