Multiple user reconfigurable CDMA processor
    1.
    发明授权
    Multiple user reconfigurable CDMA processor 失效
    多用户可重配置CDMA处理器

    公开(公告)号:US07031372B2

    公开(公告)日:2006-04-18

    申请号:US10964114

    申请日:2004-10-13

    IPC分类号: H04L27/30

    CPC分类号: H04B1/707

    摘要: A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

    摘要翻译: 与本发明的某些实施例一致的电路具有N个参考时钟频率(230)的源,其中N是大于1的整数。 N个扩展器电路(954)接收N个参考时钟频率并从其产生N个频率扩展的输出时钟信号。 多个N种子花式(958)产生N个种子更新值。 多个N个种子寄存器(962)各自接收N个种子更新值中的一个并从其生成N个种子掩码。 多个N个逻辑电路(966)分别接收N个种子掩码和N个频率扩展输出时钟信号之一。 N个逻辑电路(966)中的每一个从种子掩码和频率扩展输出时钟信号产生伪随机序列。 该摘要不被认为是限制性的,因为其他实施例可能偏离本摘要中描述的特征。

    Digital predistortion system for linearizing a power amplifier
    2.
    发明授权
    Digital predistortion system for linearizing a power amplifier 有权
    用于线性化功率放大器的数字预失真系统

    公开(公告)号:US06937669B2

    公开(公告)日:2005-08-30

    申请号:US10308831

    申请日:2002-12-03

    IPC分类号: H03F1/32 H04L27/36 H04L25/49

    CPC分类号: H03F1/3247 H04L27/368

    摘要: A predistortion linear power amplifier utilizes several predistortion computation engines to receive a first carrier signal. The predistortion computation engines also receive input from a predistortion algorithm engine. The predistortion algorithm engine receives its data from a predistortion amplifier sensor that monitors the operating characteristics of the amplifier and also from a feedback control circuit that provides frequency correlated input and feedback data. The processed data from the predistortion algorithm engine is then input into the predistortion computation engine along with the carrier signal. An output combiner circuit takes the output of each predistortion computation engine and generates a single correction estimate, which is then input into the nonlinear amplifier for producing a substantially linear output signal.

    摘要翻译: 预失真线性功率放大器利用若干预失真计算引擎来接收第一载波信号。 预失真计算引擎还从预失真算法引擎接收输入。 预失真算法引擎从预失真放大器传感器接收其数据,该预失真放大器传感器监视放大器的工作特性,并且还提供提供频率相关输入和反馈数据的反馈控制电路。 然后将来自预失真算法引擎的处理后的数据与载波信号一起输入到预失真计算引擎中。 输出组合器电路获取每个预失真计算引擎的输出并产生单个校正估计,然后输入到非线性放大器中以产生基本线性的输出信号。