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公开(公告)号：US07031372B2
公开(公告)日：2006-04-18
申请号：US10964114
申请日：2004-10-13
IPC分类号： H04L27/30
CPC分类号： H04B1/707
摘要： A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
摘要翻译： 与本发明的某些实施例一致的电路具有N个参考时钟频率（230）的源，其中N是大于1的整数。 N个扩展器电路（954）接收N个参考时钟频率并从其产生N个频率扩展的输出时钟信号。 多个N种子花式（958）产生N个种子更新值。 多个N个种子寄存器（962）各自接收N个种子更新值中的一个并从其生成N个种子掩码。 多个N个逻辑电路（966）分别接收N个种子掩码和N个频率扩展输出时钟信号之一。 N个逻辑电路（966）中的每一个从种子掩码和频率扩展输出时钟信号产生伪随机序列。 该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。
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2.发明申请公开(公告)号：US20080095291A1
公开(公告)日：2008-04-24
申请号：US11584410
申请日：2006-10-19
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H04L7/0012
摘要： A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.
摘要翻译： 公开了用于编程直接数字合成器的时钟数据恢复的系统和方法。 计数器用于计算接收到的数字信号的时钟频率的粗略测量，采用分接延迟线来计算接收的数字信号的时钟频率的精细测量。 粗略和精细的测量用于计算用于编程直接数字合成器的值以产生作为接收的数字信号的时钟频率的近似副本的时钟信号。
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公开(公告)号：US08339295B2
公开(公告)日：2012-12-25
申请号：US11831465
申请日：2007-07-31
IPC分类号： H03M1/48
CPC分类号： H03B21/02 , H03L7/0814
摘要： A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.
摘要翻译： 提供了一种用于管理数字到时间转换（DTC）的方法和系统。 该方法包括接收第一射频（RF）信号和第二RF信号。 第二RF信号是相移的第一RF信号。 该方法还包括将第一RF信号转换为第一中频（IF）信号，将第二RF信号转换为第二IF信号。 此外，基于时差测量技术来估计第一IF信号与第二IF信号之间的时间延迟。 基于估计的时间延迟来处理第二RF信号以补偿与第二RF信号相关联的延迟误差。
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公开(公告)号：US20090033384A1
公开(公告)日：2009-02-05
申请号：US11831465
申请日：2007-07-31
IPC分类号： H03L7/06
CPC分类号： H03B21/02 , H03L7/0814
摘要： A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.
摘要翻译： 提供了一种用于管理数字到时间转换（DTC）的方法和系统。 该方法包括接收第一射频（RF）信号和第二RF信号。 第二RF信号是相移的第一RF信号。 该方法还包括将第一RF信号转换为第一中频（IF）信号，将第二RF信号转换为第二IF信号。 此外，基于时差测量技术来估计第一IF信号和第二IF信号之间的时间延迟。 基于估计的时间延迟来处理第二RF信号以补偿与第二RF信号相关联的延迟误差。
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5.发明授权Method and apparatus for fast frequency locking in a closed loop based frequency synthesizer 有权用于在基于闭环的频率合成器中快速锁定的方法和装置公开(公告)号：US08427205B1
公开(公告)日：2013-04-23
申请号：US13328240
申请日：2011-12-16
CPC分类号： H03L7/0814
摘要： A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.
摘要翻译： 合成器包括第一处理单元，其接收与合成器的所需最终频率有关的数字信息，并确定主频率值和相应的倍频器模式。 主合成器接收主要频率值和外部参考频率信号以产生主要频率的信号。 合成器还包括接收主频率值的第二处理单元，确定对应于主频率值的预充电电压值，并响应于主频率的变化将预充电电压值发送到延迟锁定回路 频率值。 延迟锁定环接收主频率和预充电值的信号。 通过打开和关闭延迟锁定环以获得合成器的快速锁定，将DLL预充电到预充电电压值预定时间。
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6.发明授权公开(公告)号：US07773713B2
公开(公告)日：2010-08-10
申请号：US11584410
申请日：2006-10-19
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H04L7/0012
摘要： A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.
摘要翻译： 公开了用于编程直接数字合成器的时钟数据恢复的系统和方法。 计数器用于计算接收到的数字信号的时钟频率的粗略测量，采用分接延迟线来计算接收的数字信号的时钟频率的精细测量。 粗略和精细的测量用于计算用于编程直接数字合成器的值以产生作为接收的数字信号的时钟频率的近似副本的时钟信号。
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公开(公告)号：US07620133B2
公开(公告)日：2009-11-17
申请号：US10983447
申请日：2004-11-08
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , H03K5/133 , H03K5/135 , H03K2005/00286 , H03L7/0812 , H04L7/0337
摘要： A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.
摘要翻译： DPC（300）包括：用于产生时钟信号的频率源（310）; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于生成包括顺序逻辑设备（500,510,520）和组合网络的输出信号的加窗选择电路。 一种在DPC中使用的方法包括：基于识别延迟线上的第一输出抽头的期望输出信号接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头以接收至少两个不同的相移时钟信号; 以及基于所述控制信号和所接收的基本上是所需输出信号的相移时钟信号来产生（420）输出信号。
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8.发明授权Direct digital synthesizer with variable reference for improved spurious performance 有权具有可变参考的直接数字合成器，可提高杂散性能公开(公告)号：US07570096B2
公开(公告)日：2009-08-04
申请号：US11861860
申请日：2007-09-26
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/131 , H03K2005/00065 , H03L7/1806
摘要： Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.
摘要翻译： 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。
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9.发明授权Direct digital synthesizer with variable reference for improved spurious performance 有权具有可变参考的直接数字合成器，可提高杂散性能公开(公告)号：US07315215B2
公开(公告)日：2008-01-01
申请号：US11370689
申请日：2006-03-08
IPC分类号： H03L7/08
CPC分类号： H03H11/265 , H03K5/131 , H03K2005/00065 , H03L7/1806
摘要： Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.
摘要翻译： 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。
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10.发明申请DIRECT DIGITAL SYNTHESIZER WITH VARIABLE REFERENCE FOR IMPROVED SPURIOUS PERFORMANCE 有权具有可改善性能的可变参考的直接数字合成器公开(公告)号：US20080258791A1
公开(公告)日：2008-10-23
申请号：US11861860
申请日：2007-09-26
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/131 , H03K2005/00065 , H03L7/1806
摘要： Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.
摘要翻译： 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。
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