公开(公告)号：US08200939B2

公开(公告)日：2012-06-12

申请号：US12068009

申请日：2008-01-31

申请人： Edvard Sørgård ,  Jørn Nystad ,  Androas Due Engh-Halstvedt

发明人： Edvard Sørgård ,  Jørn Nystad ,  Androas Due Engh-Halstvedt

IPC分类号： G06F12/00

CPC分类号： G06F12/1027

摘要： A memory management arrangement includes a memory management unit, a cache memory and a queue arrangement. The queue is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache, the memory management unit operates to place the failed memory access request in the replay queue, and allows subsequent memory access requests to continue. The failed memory access requests in the queue are then continuously circulated through the memory management unit from the queue alternately with new memory access requests from other access initiators.

摘要翻译： 存储器管理装置包括存储器管理单元，高速缓冲存储器和队列排列。 队列是先入先出（FIFO）缓冲器，其可以排队失败的存储器访问请求，并且经由总线5将其作为输入返回到存储器管理单元，以在稍后的时间重试存储器管理单元。 如果发送到存储器管理单元的存储器访问请求经历高速缓存“未命中”，而不是阻塞存储器访问请求，直到所需的地址数据被加载到高速缓存中，则存储器管理单元操作以将失败的存储器访问请求置于 重播队列，并允许后续内存访问请求继续。 队列中的故障存储器访问请求随后通过存储器管理单元从其他访问发起者交替地循环通过新的存储器访问请求。