公开(公告)号：US20050055615A1

公开(公告)日：2005-03-10

申请号：US10731714

申请日：2003-12-09

申请人： Anupama Agashe ,  Nikila Krishnamoorthy ,  Anlndya Saha ,  Rubin Parekhji

发明人： Anupama Agashe ,  Nikila Krishnamoorthy ,  Anlndya Saha ,  Rubin Parekhji

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318552

摘要： A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.

摘要翻译： 本文公开了嵌入在具有VLCT平台的扫描架构的SoC上的扫描测试电路设计。 该BIST电路设计不受所支持的扫描测试端口数量的限制，包括至少一个具有耦合以接收测试激励数据的相应时钟域的扫描链组。 每个扫描链组具有对应的测试模式信号，以从其对应的时钟域导出的移位时钟速率移动测试激励数据。 控制解复用器连接到每个扫描链组内的每个多路复用器单元，以提供用于在测试刺激中移位的控制信号。 时钟控制机制为每个扫描链提供控制信号，以移动测试刺激并捕获结果数据。 此外，当启用同时测试模式信号时，时钟控制机制耦合到每个扫描链以实现每个扫描链组的同时捕获。