公开(公告)号：US20060248320A1

公开(公告)日：2006-11-02

申请号：US11117723

申请日：2005-04-29

申请人： Ann Chin ,  David Williamson

发明人： Ann Chin ,  David Williamson

IPC分类号： G06F9/44

CPC分类号： G06F9/3875 ,  G06F9/3836 ,  G06F9/3857

摘要： A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processing unit for executing the sequence of instructions, the processing unit comprising at least a first processing path and a second processing path to enable at least two instructions of the sequence to be executed in parallel. When executing instructions in parallel, the first processing path executes an instruction which is earlier in the sequence than the instruction executing in the second processing path. The processing unit is operable when executing a multiple iteration instruction to allow a first iteration of the multiple iteration instruction to be executed in either the first processing path or the second processing path, but to cause all remaining iterations of the multiple iteration instruction to be executed in the first processing path. This provides a particularly efficient technique for executing the sequence of instructions.

摘要翻译： 提供了一种用于执行包括至少一个多次迭代指令的指令序列的数据处理装置和方法。 数据处理装置包括用于存储指令序列的指令存储器和用于执行指令序列的处理单元，所述处理单元至少包括第一处理路径和第二处理路径，以使得能够执行该序列的至少两个指令 并行执行 当并行执行指令时，第一处理路径执行在序列中比在第二处理路径中执行的指令更早的指令。 当执行多次迭代指令以允许多次迭代指令的第一次迭代在第一处理路径或第二处理路径中执行时，处理单元可操作，而是使多个迭代指令的所有剩余迭代被执行 在第一个处理路径。 这提供了用于执行指令序列的特别有效的技术。

公开(公告)号：US20060242221A1

公开(公告)日：2006-10-26

申请号：US11114238

申请日：2005-04-26

申请人： Micah McDaniel ,  Ann Chin ,  Daniel Kershaw

发明人： Micah McDaniel ,  Ann Chin ,  Daniel Kershaw

IPC分类号： G06F7/50

CPC分类号： G06F7/509 ,  G06F7/607

摘要： A data processing apparatus operable to sum data values said data processing apparatus comprising: a plurality of adder logic stages arranged in parallel with each other; control logic operable in response to receipt of a request to sum two data values to forward portions of said two data values to respective ones of said plurality of adder logic stages, such that a first adder logic stage receives a predetermined number of lowest significant bits from each of said two data values and subsequent adder logic stages receive said predetermined number of successively higher significant bits from each of said two data values, each of said plurality of adder logic stages being operable to perform a carry propagate addition of said received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages operable to receive said intermediate sums, carries and propagate values generated from said plurality of adder logic stages and to combine said received intermediate sums, carries and propagate values to produce a sum of said two data values; wherein said control logic is operable in response to receipt of a request to add a third data value to said sum of said two data values, received before said further logic has completed said sum, to forward portions of said third data value to respective ones of said plurality of adder logic stages and to feedback said intermediate sums generated by said plurality of adder logic stages and to selectively feedback a carry generated from a preceding adder logic stage; and said plurality of adder logic stages are operable to perform a carry propagate addition of said fedback intermediate sums and carrys with respective portions of said third data value to generate a plurality of further intermediate sums, further carrys and further propagate values; and wherein said further logic stages are operable to receive said plurality of further intermediate sums, further carries and further propagate values and to combine said received further intermediate sums, carries and propagate values to produce a sum of said three data values.