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公开(公告)号：US08700688B2
公开(公告)日：2014-04-15
申请号：US12379447
申请日：2009-02-23
CPC分类号： G06F9/3001 , G06F7/726
摘要： A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.
摘要翻译： 数据处理系统2包括响应多项式除法指令DIVL.PN以产生控制处理电路26执行多项式除法运算的控制信号的指令译码器22。 分母多项式由存储在寄存器中的分母值表示，假设多项式的最高度项总是具有系数“1”，使得该系数不需要存储在存储分母值的寄存器中，因此 分母多项式可以具有比存储分母值的寄存器内的位空间更高的程度。 多项式除法指令返回分别表示商多项式和余数多项式的商值和余数值。
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公开(公告)号：US07886098B2
公开(公告)日：2011-02-08
申请号：US11898640
申请日：2007-09-13
申请人： Daniel Kershaw , Stuart David Biles
发明人： Daniel Kershaw , Stuart David Biles
CPC分类号： G06F12/1416 , G06F12/1491
摘要： A data processing apparatus and method for generating access requests is provided. A bus master is provided which can operate either in a secure domain or a non-secure domain of the data processing apparatus, according to a signal received from external to the bus master. The signal is generated to be fixed during normal operation of the bus master. Control logic is provided which, when the bus master device is operating in a secure domain, is operable to generate a domain specifying signal associated with an access request generated by the bus master core indicating either secure or non-secure access, in dependence on either a default memory map or securely defined memory region descriptors. Thus, the bus master operating in a secure domain can generate both secure and non-secure accesses, without itself being able to switch between secure and non-secure operation.
摘要翻译： 提供了一种用于产生访问请求的数据处理装置和方法。 根据从总线主机外部接收的信号，提供可以在数据处理装置的安全域或非安全域中操作的总线主机。 在总线主机的正常工作期间，生成固定信号。 提供控制逻辑，当总线主设备在安全域中操作时，可以根据总线主机核心生成的指示安全或非安全访问的访问请求产生一个域指定信号， 默认内存映射或安全定义的内存区域描述符。 因此，在安全域中操作的总线主机可以生成安全和非安全访问，而无需在安全和非安全操作之间进行切换。
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公开(公告)号：US07668897B2
公开(公告)日：2010-02-23
申请号：US10461880
申请日：2003-06-16
申请人： Daniel Kershaw
发明人： Daniel Kershaw
IPC分类号： G06F7/38
CPC分类号： G06F9/3001
摘要： Within a processor 2 providing single instruction multiple data (SIMD) type operation, single data processing instructions can serve to control processing logic 4, 6, 8, 10 to perform SIMD-type processing operations upon multiple independent input values to generate multiple independent result values having a greater data width than the corresponding input values. A repartitioner (FIG. 5) in the form of appropriately controlled multiplexers serves to partition these result data values into high order bit portions and low order bit portions that are stored into separate registers 38, 40. The required SIMD width preserved result values can be read from the desired high order 38 result register or low order result register 40 without further processing being required. Furthermore, the preservation of the full result facilitates improvements in accuracy, such as over extended accumulate operations and the like.
摘要翻译： 在提供单指令多数据（SIMD）类型操作的处理器2中，单个数据处理指令可以用于控制处理逻辑4,6,8,10以在多个独立输入值上执行SIMD型处理操作，以产生多个独立结果值 具有比相应的输入值更大的数据宽度。 以适当控制的多路复用器形式的重新分配器（图5）用于将这些结果数据值分割成存储在单独的寄存器38,40中的高位位部分和低位位部分。所需的SIMD宽度保留结果值可以是 从期望的高阶38结果寄存器或低阶结果寄存器40读取，而不需要进一步的处理。 此外，保持全部结果有助于提高精度，例如过度扩展累积操作等。
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公开(公告)号：US20080046762A1
公开(公告)日：2008-02-21
申请号：US11889644
申请日：2007-08-15
IPC分类号： G06F12/14
摘要： A data processing apparatus and method for protecting system control registers is provided. Processing logic is providing for executing software routines and a plurality of system control registers are used to store access control information for a plurality of system resources available to the processing logic when executing at least some of those software routines. Additionally, at least one write control register is provided, with each field of that register being associated with one or more of the system control registers. Disable control logic is used to generate a disable signal, and when that disable signal is clear access control information can be written into the system control registers, and write restriction data can be written into each of the fields of the at least one write control register. Then, when the disable control logic sets the disable signal, the at least one write control register becomes read only, and for each field that has write restriction data therein those associated system control registers indicated by the write restriction data also become read only. This mechanism provides a very flexible approach for programming which system control registers are to be treated as read only registers.
摘要翻译： 提供一种用于保护系统控制寄存器的数据处理装置和方法。 处理逻辑正在提供执行软件程序，并且当执行这些软件程序中的至少一些时，多个系统控制寄存器用于存储可用于处理逻辑的多个系统资源的访问控制信息。 此外，提供至少一个写入控制寄存器，该寄存器的每个字段与一个或多个系统控制寄存器相关联。 禁止控制逻辑用于产生禁用信号，当禁用信号清除时，访问控制信息可以写入系统控制寄存器，写入限制数据可写入至少一个写入控制寄存器的每个字段 。 然后，当禁用控制逻辑设置禁止信号时，至少一个写入控制寄存器变为只读，并且对于其中具有写入限制数据的每个字段，由写入限制数据指示的那些相关联的系统控制寄存器也变为只读。 这种机制提供了非常灵活的编程方式，哪些系统控制寄存器被视为只读寄存器。
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公开(公告)号：US20070220276A1
公开(公告)日：2007-09-20
申请号：US11376733
申请日：2006-03-16
申请人： Daren Croxford , Donald Felton , Daniel Kershaw , Peter Wilson
发明人： Daren Croxford , Donald Felton , Daniel Kershaw , Peter Wilson
IPC分类号： H04N7/16 , H04L9/32 , G06F12/14 , G06F17/30 , G06F7/04 , H04L9/00 , G06F11/30 , G06K9/00 , H04K1/00 , H03M1/68
CPC分类号： G06F21/79 , G06F12/145 , G06F21/74
摘要： A data processing apparatus and method are provided for managing access to content within the data processing apparatus. The data processing apparatus has a secure domain and a non-secure domain and comprises at least one device which is operable when seeking to access content stored in memory to issue a memory access request pertaining to either the secure domain or the non-secure domain. Further, writeable memory is provided which can store content required by the at least one device, with the writeable memory having at least one read only region whose content is stored therein under control of a secure task, the secure task being a task executed by one of the devices in the secure domain. Protection logic is then used in association with the writeable memory, which on receipt of a memory access request seeking to access content in the at least one read only region, prevents access to that read only region if that memory access request pertains to the non-secure domain and is seeking to write content to the read only region. This enables the speed, power and flexibility benefits of placing content in writeable memory to be achieved without prejudicing the security of that content, by ensuring that that content cannot be modified from the non-secure domain.
摘要翻译： 提供了一种用于管理对数据处理装置内的内容的访问的数据处理装置和方法。 数据处理装置具有安全域和非安全域，并且包括至少一个设备，当设法访问存储在存储器中的内容以发布与安全域或非安全域相关的存储器访问请求时可操作。 此外，提供可写存储器，其可以存储至少一个设备所需的内容，其中可写存储器具有至少一个只读区域，其内容在安全任务的控制下存储在其中，该安全任务是由一个执行的任务 的安全域中的设备。 然后，与可写存储器相关联地使用保护逻辑，其在接收到寻求访问所述至少一个只读区域中的内容的存储器访问请求时，如果该存储器访问请求涉及非可读存储器访问请求， 并且正在寻求将内容写入只读区域。 这使得通过确保不能从非安全域修改该内容，可以实现将内容放置在可写入内存中的速度，功率和灵活性，而不会影响该内容的安全性。
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公开(公告)号：US20060294248A1
公开(公告)日：2006-12-28
申请号：US11168957
申请日：2005-06-28
申请人： Daniel Kershaw
发明人： Daniel Kershaw
IPC分类号： G06F15/16
CPC分类号： H04L67/34 , H04L65/1006
摘要： A communications server is provided that is able to receive a Session Initiation Protocol (SIP) message, and access SIP client-specific information within the SIP message. The client specific information can be provided in a user agent header. The server automatically adapts its interaction with the SIP client based on the client-specific information. A method of automatically configuring a communications server is also provided.
摘要翻译： 提供能够接收会话发起协议（SIP）消息并且在SIP消息内访问SIP客户端特定信息的通信服务器。 可以在用户代理头部中提供客户端特定信息。 服务器根据客户端特定的信息自动适应与SIP客户端的交互。 还提供了一种自动配置通信服务器的方法。
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公开(公告)号：US20060242221A1
公开(公告)日：2006-10-26
申请号：US11114238
申请日：2005-04-26
申请人： Micah McDaniel , Ann Chin , Daniel Kershaw
发明人： Micah McDaniel , Ann Chin , Daniel Kershaw
IPC分类号： G06F7/50
摘要： A data processing apparatus operable to sum data values said data processing apparatus comprising: a plurality of adder logic stages arranged in parallel with each other; control logic operable in response to receipt of a request to sum two data values to forward portions of said two data values to respective ones of said plurality of adder logic stages, such that a first adder logic stage receives a predetermined number of lowest significant bits from each of said two data values and subsequent adder logic stages receive said predetermined number of successively higher significant bits from each of said two data values, each of said plurality of adder logic stages being operable to perform a carry propagate addition of said received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages operable to receive said intermediate sums, carries and propagate values generated from said plurality of adder logic stages and to combine said received intermediate sums, carries and propagate values to produce a sum of said two data values; wherein said control logic is operable in response to receipt of a request to add a third data value to said sum of said two data values, received before said further logic has completed said sum, to forward portions of said third data value to respective ones of said plurality of adder logic stages and to feedback said intermediate sums generated by said plurality of adder logic stages and to selectively feedback a carry generated from a preceding adder logic stage; and said plurality of adder logic stages are operable to perform a carry propagate addition of said fedback intermediate sums and carrys with respective portions of said third data value to generate a plurality of further intermediate sums, further carrys and further propagate values; and wherein said further logic stages are operable to receive said plurality of further intermediate sums, further carries and further propagate values and to combine said received further intermediate sums, carries and propagate values to produce a sum of said three data values.
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公开(公告)号：US07020751B2
公开(公告)日：2006-03-28
申请号：US10201955
申请日：2002-07-25
申请人： Daniel Kershaw
发明人： Daniel Kershaw
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0804 , G06F13/18
摘要： A data processing system 2 is described including a cache memory 8 and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32 within a cache controller 10 selects victim cache storage lines 28 upon a cache miss such that unlocked cache storage lines are selected in preference to locked cache storage lines, non-dirty cache storage lines are selected in preference to dirty cache storage lines, and cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM storage bank. A DRAM controller 24 is provided that continuously performs a background processing operation whereby dirty cache storage lines 28 within a cache memory 8 are written back to their respective DRAM banks 16, 18, 20, 22 when these are not busy performing other operations and when the cache storage line has a least recently used value below a certain threshold. A bus arbitration circuit 12 is provided that re-arbitrates bus master priorities in dependence upon determined latencies for respective memory access requests. As an example, if a high priority memory access request results a cache miss, with a lower priority memory access request resulting in a cache hit, then the lower priority memory access request will be re-arbitrated to be performed ahead of the normally higher priority memory access request and may be finished before that higher priority memory access request starts to return data words to a data bus 14.
摘要翻译： 描述了数据处理系统2，其包括高速缓存存储器8和多个DRAM存储体18,18,20,22。 高速缓存控制器10内的受害者选择电路32在高速缓存未命中时选择受害者高速缓存存储线28，以便优先选择锁定的高速缓存存储线来解锁高速缓存存储线，优先选择非脏高速缓存存储线， 选择需要写入非忙DRAM库的高速缓存存储线，优先于需要向忙DRAM存储库写回的高速缓存存储线。 提供DRAM控制器24，其连续执行后台处理操作，由此当高速缓存存储器8内的脏高速缓存存储线28在其不忙于执行其他操作时被写回到它们各自的DRAM存储体16,18,20,22，并且当 高速缓存存储线具有低于一定阈值的最近最近使用的值。 提供总线仲裁电路12，其根据对于各个存储器访问请求的确定的延迟重新仲裁总线主机优先级。 作为示例，如果高优先级存储器访问请求导致高速缓存未命中，则优先级较低的存储器访问请求导致高速缓存命中，则优先级较低的存储器访问请求将被重新仲裁以在正常较高优先级之前执行 存储器访问请求，并且可以在更高优先级的存储器访问请求开始将数据字返回到数据总线14之前完成。
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公开(公告)号：US20050210089A1
公开(公告)日：2005-09-22
申请号：US10804181
申请日：2004-03-19
申请人： Daniel Kershaw , Micah McDaniel
发明人： Daniel Kershaw , Micah McDaniel
CPC分类号： G06F7/49921
摘要： A saturating shifter is provided which operates to detect in parallel with a shifting operation whether the result of that shifting operation will require saturating. If saturation is required, then the necessary saturating mask may be determined earlier and accordingly processing speed increased.
摘要翻译： 提供饱和移动器，其操作以与移位操作并行地检测，移位操作的结果是否需要饱和。 如果需要饱和，则可以更早地确定必要的饱和掩模，并且相应地提高处理速度。
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公开(公告)号：US20050125638A1
公开(公告)日：2005-06-09
申请号：US10889365
申请日：2004-07-13
申请人： Simon Ford , Dominic Symes , Daniel Kershaw
发明人： Simon Ford , Dominic Symes , Daniel Kershaw
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/3016 , G06F9/30167
摘要： A data processing apparatus and method. The data processing apparatus comprising: a register data store operable to store data elements; an instruction decoder operable to decode a shift instruction; a data processor operable to perform data processing operations controlled by said instruction decoder wherein: in response to said decoded shift instruction, said data processor is operable to specify within said register data store, one or more source registers operable to store a plurality of source data elements of a first size, and one or more destination registers operable to store a corresponding plurality of resultant data elements of a second size, said second size not being equal to said first size; and to perform the following operations in parallel on said plurality of source data elements to produce said corresponding plurality of resultant data elements: shift each of said plurality of source data elements a specified number of places; form at least a part of each of said resultant data elements from information derived from at least a portion of a corresponding one of said plurality of source data elements; store said resultant data elements in said destination register.
摘要翻译： 一种数据处理装置和方法。 该数据处理装置包括：可操作以存储数据元素的寄存器数据存储器; 指令解码器，用于解码移位指令; 数据处理器，用于执行由所述指令解码器控制的数据处理操作，其中：响应于所述解码的移位指令，所述数据处理器可操作以在所述寄存器数据存储器内指定一个或多个源寄存器，其可操作以存储多个源数据 以及一个或多个目的地寄存器，其可操作以存储第二大小的相应多个结果数据元素，所述第二大小不等于所述第一大小; 并且在所述多个源数据元素上并行地执行以下操作以产生所述相应的多个结果数据元素：将所述多个源数据元素中的每一个移位指定数目的位置; 根据从所述多个源数据元素中相应的一个源数据元素的至少一部分导出的信息，形成每个所述结果数据元素的至少一部分; 将所述结果数据元素存储在所述目的地寄存器中。
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