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公开(公告)号：US20190087876A1
公开(公告)日：2019-03-21
申请号：US16195165
申请日：2018-11-19
申请人： Anthony M. Jones
发明人： Anthony M. Jones
IPC分类号： G06Q30/02 , G06F3/0481 , G06F16/958 , G06F16/9535 , G06F3/0484
摘要： Disclosed embodiments include a consumer display system that may include the use of a main gauge, sometimes resembling a digital gasoline gauge of a vehicle, such that the main gauge displays an analog and/or digital value to comport with an overall score derived from user input into a plurality of categories.
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公开(公告)号：US20160364775A1
公开(公告)日：2016-12-15
申请号：US15249004
申请日：2016-08-26
申请人： Anthony M. Jones
发明人： Anthony M. Jones
IPC分类号： G06Q30/02 , G06F17/30 , G06F3/0481
CPC分类号： G06Q30/0282 , G06F3/04817 , G06F16/26 , G06F16/9535 , G06F16/958
摘要： Disclosed embodiments include a consumer display system that may include the use of a main gauge, sometimes resembling a digital gasoline gauge of a vehicle, such that the main gauge displays an analog and/or digital value to comport with an overall score derived from user input into a plurality of categories.
摘要翻译： 公开的实施例包括消费者显示系统，其可以包括使用主计量器，有时类似于车辆的数字汽油计，使得主计量器显示模拟和/或数字值以与来自用户输入的总得分相匹配 分成多个类别。
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3.发明授权公开(公告)号：US07408520B2
公开(公告)日：2008-08-05
申请号：US11303345
申请日：2005-12-16
IPC分类号： H01Q13/10
CPC分类号： H01Q21/065 , H01Q1/38
摘要： The slot-mode antenna includes an array of slot antenna units carried by a substrate, and each slot antenna unit has a pair of patch antenna elements arranged in laterally spaced apart relation about at least one central feed position. Adjacent patch antenna elements of adjacent slot-mode antenna units include respective spaced apart edge portions defining gaps therebetween, and a capacitive coupling layer or plates overlap the respective spaced apart edge portions to provide increased capacitive coupling therebetween. The capacitive coupling layer may include continuous or periodic capacitive coupling plates along each gap defined by the respective spaced apart edge portions.
摘要翻译： 时隙模式天线包括由衬底承载的缝隙天线单元的阵列，并且每个缝隙天线单元具有围绕至少一个中心馈送位置以横向间隔开的关系布置的一对贴片天线元件。 相邻槽模式天线单元的相邻贴片天线元件包括在其间限定间隙的相应的间隔开的边缘部分，并且电容耦合层或板与相应的间隔开的边缘部分重叠以在其间提供增加的电容耦合。 电容耦合层可以包括沿着由相应间隔开的边缘部分限定的每个间隙的连续的或周期性的电容耦合板。
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4.发明授权公开(公告)号：US07084827B1
公开(公告)日：2006-08-01
申请号：US11052579
申请日：2005-02-07
CPC分类号： H01Q1/286 , H01Q9/285 , H01Q15/0013 , H01Q21/062 , H01Q21/20
摘要： An antenna includes a substrate, and an array of dipole antenna elements on the substrate. Each dipole antenna element includes a medial feed portion and a pair of legs extending outwardly therefrom. Adjacent legs of adjacent dipole antenna elements include respective spaced apart end portions with impedance coupling therebetween. An impedance matching layer is adjacent a side of the array of dipole antenna elements opposite the substrate. The impedance matching layer includes an array of spaced apart conductive elements.
摘要翻译： 天线包括衬底和衬底上的偶极天线元件阵列。 每个偶极天线元件包括中间馈送部分和从其向外延伸的一对腿。 相邻偶极天线元件的相邻支腿包括各自间隔开的端部，其间具有阻抗耦合。 阻抗匹配层邻近与衬底相对的偶极天线元件阵列的一侧。 阻抗匹配层包括间隔开的导电元件阵列。
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公开(公告)号：US06977623B2
公开(公告)日：2005-12-20
申请号：US10780268
申请日：2004-02-17
CPC分类号： H01Q13/106 , H01Q21/0006 , H01Q21/062
摘要： A phased array antenna includes a substrate, and a patterned conductive layer is on the substrate. The patterned conductive layer defines a plurality of slotted dipole antenna elements each having a medial feed portion associated therewith. Each slotted dipole antenna element includes a pair of slotted legs extending outwardly from the medial feed portion. Pairs of adjacent slotted legs of adjacent slotted dipole antenna elements include respective spaced apart end portions having predetermined shapes and relative positioning to provide increased inductive coupling between the adjacent slotted dipole antenna elements.
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6.发明授权Multiband radially distributed graded phased array antenna and associated methods 有权多频段分布式分级相控阵天线及相关方法公开(公告)号：US06954179B2
公开(公告)日：2005-10-11
申请号：US10702899
申请日：2003-11-06
IPC分类号： H01Q1/38 , H01Q3/24 , H01Q3/26 , H01Q3/30 , H01Q5/00 , H01Q5/40 , H01Q9/28 , H01Q19/10 , H01Q21/06 , H01Q21/00 , H01Q1/00
摘要： A phased array antenna includes a substrate, and dipole element arrays extending outwardly from an imaginary center point on the substrate. Each dipole element array includes dipole antenna elements arranged in an end-to-end relation and has different dipole sizes for dipole antenna elements in a direction extending outwardly from the imaginary center point. The different spacing between the ground plane and the dipole element arrays increases from the imaginary center point towards an edge of the substrate.
摘要翻译： 相控阵天线包括衬底和从衬底上的假想中心点向外延伸的偶极子阵列。 每个偶极子元件阵列包括以端对端关系布置的偶极天线元件，并且在从假想中心点向外延伸的方向上具有用于偶极天线元件的不同偶极子尺寸。 接地平面和偶极子阵列之间的不同间距从假想中心点向衬底边缘增加。
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公开(公告)号：US06171407B2
公开(公告)日：2001-01-09
申请号：US09415075
申请日：1999-10-12
IPC分类号： B08B1300
CPC分类号： B08B15/007
摘要： An apparatus and method are provided for removing gases produced during off-service cleaning of a processing chamber which operates under vacuum in a wafer fabrication tool. The apparatus includes a ventilation fixture providing a manifold having an internal cavity in fluid communication with a source of vacuum and at least one intake aperture, and a quick disconnect fitting connected to the source of vacuum and in fluid communication with the internal cavity. The manifold is portable and located adjacent to the processing chamber during cleaning.
摘要翻译： 提供了一种用于去除在晶片制造工具中在真空下操作的处理室的非工作状态清洁期间产生的气体的装置和方法。 该设备包括通风夹具，其提供具有与真空源和至少一个进气孔流体连通的内腔的歧管，以及连接到真空源并与内腔流体连通的快速断开配件。 歧管是便携式的，并且在清洁期间位于处理室附近。
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公开(公告)号：US5617458A
公开(公告)日：1997-04-01
申请号：US567555
申请日：1995-12-05
申请人： Anthony M. Jones , David A. Barnes
发明人： Anthony M. Jones , David A. Barnes
CPC分类号： H03K5/15026 , G06F1/08
摘要： The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.
摘要翻译： 本发明公开了一种与L个计数器结合实现L相时钟的方法和装置，其中L是一个整数，以L可缩放的频率进行计数。
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公开(公告)号：US5596517A
公开(公告)日：1997-01-21
申请号：US400722
申请日：1995-03-07
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
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10.发明授权
公开(公告)号：US5594678A
公开(公告)日：1997-01-14
申请号：US400723
申请日：1995-03-07
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT或逆离散余弦变换方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。 在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。 在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT + E，rad 2 + EE，并且奇数输入字在公共处理步骤中处理之前成对地相加。 在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。 在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。 输入值优选地向上扩展2ROOT + E，rad 2 + EE的因子。 通过强制这些位为“1”或“0”可选地调整一些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。 该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。
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