公开(公告)号：US5747369A

公开(公告)日：1998-05-05

申请号：US782706

申请日：1997-01-13

申请人： Arjun Kumar Kantimahanti ,  Chivukula Subrahmanyam ,  Mei Sheng Zhou

发明人： Arjun Kumar Kantimahanti ,  Chivukula Subrahmanyam ,  Mei Sheng Zhou

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L27/0629

摘要： A method is described for forming capacitors in integrated circuits by making the capacitors concurrently with the fabrication of the interconnection wiring levels. A single additional photolithographic step and two depositions are required to form capacitors within each wiring level. A key feature of the invention is the use of an etch-stop to protect the capacitor dielectric during contact or via etching. The storage plates of the capacitor are formed from two successive conductor levels which can include polysilicon levels as well. The process is particularly suited to the manufacture of logic circuits and can be used effectively in MOSFET, bipolar and BiCMOS processes.

摘要翻译： 描述了一种用于在集成电路中形成电容器的方法，其中通过在制造互连线路电平的同时使电容器同时进行。 需要单个附加的光刻步骤和两个沉积以在每个布线层内形成电容器。 本发明的一个关键特征是在接触或通过蚀刻期间使用蚀刻停止来保护电容器电介质。 电容器的存储板由两个连续的导体电平形成，也可以包括多晶硅层。 该过程特别适用于逻辑电路的制造，可以有效地用于MOSFET，双极和BiCMOS工艺。