公开(公告)号：US20100064116A1

公开(公告)日：2010-03-11

申请号：US12619355

申请日：2009-11-16

申请人： Arthur John Low ,  Stephen J. Davis

发明人： Arthur John Low ,  Stephen J. Davis

IPC分类号： G06F15/80 ,  G06F9/30

CPC分类号： H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

摘要： A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.

摘要翻译： 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析分组并提供包括要在数据分组上执行的进程列表及其排序的报头。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地进行下一个处理的确定，直到在其被提供给输出端口的分组没有下一个处理为止。

公开(公告)号：US07631116B2

公开(公告)日：2009-12-08

申请号：US11257525

申请日：2005-10-25

申请人： Arthur John Low ,  Stephen J. Davis

发明人： Arthur John Low ,  Stephen J. Davis

IPC分类号： G06F3/00 ,  G06F13/00 ,  H04L29/06

CPC分类号： H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

摘要： A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.

摘要翻译： 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析分组并提供包括要在数据分组上执行的进程列表及其排序的报头。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地进行下一个处理的确定，直到在其被提供给输出端口的分组没有下一个处理为止。

公开(公告)号：US08639912B2

公开(公告)日：2014-01-28

申请号：US12619355

申请日：2009-11-16

申请人： Arthur John Low ,  Stephen J. Davis

发明人： Arthur John Low ,  Stephen J. Davis

IPC分类号： G06F15/00 ,  G06F3/00

CPC分类号： H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

摘要： A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyze the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.

摘要翻译： 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析分组并提供包括要在数据分组上执行的进程列表及其排序的报头。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地进行下一个处理的确定，直到在其被提供给输出端口的分组没有下一个处理为止。

公开(公告)号：US07386705B2

公开(公告)日：2008-06-10

申请号：US10228933

申请日：2002-08-27

申请人： Arthur John Low ,  Neil Farquhar Hamilton ,  Hafid Zaabab

发明人： Arthur John Low ,  Neil Farquhar Hamilton ,  Hafid Zaabab

IPC分类号： G06F15/82

CPC分类号： H04L63/0428 ,  G06F21/72 ,  H04L9/06 ,  H04L2209/125

摘要： An apparatus for calculating and encryption of data has a multistage processing array and a plurality of registers. Each register has a status bit which indicates a “go” or “done” condition when the register is loaded. This enables the process array, after completion of a processing cycle, to connect to a “ready” register.

摘要翻译： 用于计算和加密数据的装置具有多级处理阵列和多个寄存器。 当寄存器加载时，每个寄存器都有一个状态位，表示“go”或“done”条件。 这使处理数组在处理周期完成后连接到“就绪”寄存器。

公开(公告)号：US06959346B2

公开(公告)日：2005-10-25

申请号：US09741829

申请日：2000-12-22

申请人： Arthur John Low ,  Stephen J. Davis

发明人： Arthur John Low ,  Stephen J. Davis

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  G06F3/00

CPC分类号： H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

摘要： A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list processes to perform on the packet of data and am ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is not next process for a packet at which time it is provided to an output port.

摘要翻译： 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析数据包，并提供一个报头，其中包括对数据包执行的列表进程和序列。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地确定下一个处理，直到在其被提供给输出端口的分组没有下一个处理。