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公开(公告)号：US12132665B2
公开(公告)日：2024-10-29
申请号：US17990768
申请日：2022-11-21
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Yamin Friedman , Idan Burstein , Ariel Shahar , Roee Moyal , Gil Kremer
IPC: H04L47/62 , H04L47/6275 , H04L49/90
CPC classification number: H04L47/624 , H04L47/6275 , H04L49/9036
Abstract: An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.
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公开(公告)号：US20240348539A1
公开(公告)日：2024-10-17
申请号：US18755978
申请日：2024-06-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Andrew S. Kopser , Abdulla M. Bataineh
IPC: H04L45/28 , G06F9/50 , G06F9/54 , G06F12/0862 , G06F12/1036 , G06F12/1045 , G06F13/14 , G06F13/16 , G06F13/28 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/173 , H04L1/00 , H04L43/0876 , H04L43/10 , H04L45/00 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/12 , H04L45/122 , H04L45/125 , H04L45/16 , H04L45/24 , H04L45/42 , H04L45/745 , H04L45/7453 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/34 , H04L47/52 , H04L47/62 , H04L47/625 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/78 , H04L47/80 , H04L49/00 , H04L49/101 , H04L49/15 , H04L49/90 , H04L49/9005 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/28 , H04L69/40
CPC classification number: H04L45/28 , G06F9/505 , G06F9/546 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F13/14 , G06F13/16 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F13/28 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F15/17331 , H04L1/0083 , H04L43/0876 , H04L43/10 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/122 , H04L45/123 , H04L45/125 , H04L45/16 , H04L45/20 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/42 , H04L45/46 , H04L45/566 , H04L45/70 , H04L45/745 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/18 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/323 , H04L47/34 , H04L47/39 , H04L47/52 , H04L47/621 , H04L47/6235 , H04L47/626 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/781 , H04L47/80 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/9005 , H04L49/9021 , H04L49/9036 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , G06F2212/50 , G06F2213/0026 , G06F2213/3808 , H04L69/28
Abstract: Methods and systems are provided to facilitate network ingress fairness between applications. At an ingress port of a network, the applications providing data communications are reviewed so that and arbitration process can be used to fairly allocate bandwidth at that ingress port. In a typical process, the bandwidth is allocated based upon the number of flow channels, irrespective of the source and characteristics of those flow channels. At the ingress port, an examination of the application providing the data communication will allow for a more appropriate allocation of input bandwidth.
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公开(公告)号：US20240314063A1
公开(公告)日：2024-09-19
申请号：US18675551
申请日：2024-05-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jonathan P. Beecroft , Edwin L. Froese
IPC: H04L45/28 , G06F9/50 , G06F9/54 , G06F12/0862 , G06F12/1036 , G06F12/1045 , G06F13/14 , G06F13/16 , G06F13/28 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/173 , H04L1/00 , H04L43/0876 , H04L43/10 , H04L45/00 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/12 , H04L45/122 , H04L45/125 , H04L45/16 , H04L45/24 , H04L45/42 , H04L45/745 , H04L45/7453 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/34 , H04L47/52 , H04L47/62 , H04L47/625 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/78 , H04L47/80 , H04L49/00 , H04L49/101 , H04L49/15 , H04L49/90 , H04L49/9005 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/28 , H04L69/40
CPC classification number: H04L45/28 , G06F9/505 , G06F9/546 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F13/14 , G06F13/16 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F13/28 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F15/17331 , H04L1/0083 , H04L43/0876 , H04L43/10 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/122 , H04L45/123 , H04L45/125 , H04L45/16 , H04L45/20 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/42 , H04L45/46 , H04L45/566 , H04L45/70 , H04L45/745 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/18 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/323 , H04L47/34 , H04L47/39 , H04L47/52 , H04L47/621 , H04L47/6235 , H04L47/626 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/781 , H04L47/80 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/9005 , H04L49/9021 , H04L49/9036 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , G06F2212/50 , G06F2213/0026 , G06F2213/3808 , H04L69/28
Abstract: Systems and methods are provided for “on the fly” routing of data transmissions in the presence of errors. Switches can establish flow channels corresponding to flows in the network. In response to encountering a critical error on a network link along a transmission path, a switch can generate an error acknowledgement. The switch can transmit the error acknowledgements to ingress ports upstream from the network link via the plurality of flow channels. By transmitting the error acknowledgement, it indicates that the network link where the critical error was encountered is a failed link to ingress ports upstream from the failed link. Subsequently, each ingress port upstream from the failed link can dynamically update the path of the plurality of flows that are upstream from the failed link such that the plurality of flows that are upstream from the failed link are routed in a manner that avoids the failed link.
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公开(公告)号：US12095680B2
公开(公告)日：2024-09-17
申请号：US18113885
申请日：2023-02-24
Applicant: Chicago Mercantile Exchange Inc.
IPC: H04L47/50 , H04L47/62 , H04L47/6275 , H04L49/90
CPC classification number: H04L49/9036 , H04L47/50 , H04L47/622 , H04L47/6275
Abstract: The disclosed embodiments, collectively referred to as the “Message Ordering Buffer” or “MOB”, relate to an improved messaging platform, or processing system, which may also be referred to as a message processing architecture or platform, which routes messages from a publisher to a subscriber ensuring related messages, e.g., ordered messages, are conveyed to a single recipient, e.g., processing thread, without unnecessarily committing resources of the architecture to that recipient or otherwise preventing message transmission to other recipients. The disclosed embodiments further include additional features which improve efficient and facilitate deployment in different application environments. The disclosed embodiments may be deployed as a message oriented middleware component directly installed, or accessed as a service, and accessed by publishers and subscribers, as described herein, so as to electronically exchange messages therebetween.
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公开(公告)号：US20240259301A1
公开(公告)日：2024-08-01
申请号：US18630121
申请日：2024-04-09
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Abdulla M. Bataineh , Thomas L. Court , Edwin L. Froese
IPC: H04L45/28 , G06F9/50 , G06F9/54 , G06F12/0862 , G06F12/1036 , G06F12/1045 , G06F13/14 , G06F13/16 , G06F13/28 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/173 , H04L1/00 , H04L43/0876 , H04L43/10 , H04L45/00 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/12 , H04L45/122 , H04L45/125 , H04L45/16 , H04L45/24 , H04L45/42 , H04L45/745 , H04L45/7453 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/34 , H04L47/52 , H04L47/62 , H04L47/625 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/78 , H04L47/80 , H04L49/00 , H04L49/101 , H04L49/15 , H04L49/90 , H04L49/9005 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/28 , H04L69/40
CPC classification number: H04L45/28 , G06F9/505 , G06F9/546 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F13/14 , G06F13/16 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F13/28 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F15/17331 , H04L1/0083 , H04L43/0876 , H04L43/10 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/122 , H04L45/123 , H04L45/125 , H04L45/16 , H04L45/20 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/42 , H04L45/46 , H04L45/566 , H04L45/70 , H04L45/745 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/18 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/323 , H04L47/34 , H04L47/39 , H04L47/52 , H04L47/621 , H04L47/6235 , H04L47/626 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/781 , H04L47/80 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/9005 , H04L49/9021 , H04L49/9036 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , G06F2212/50 , G06F2213/0026 , G06F2213/3808 , H04L69/28
Abstract: Systems and methods are provided for efficiently routing data through a network having a plurality of switches configured in a fat-tree topology, including: receiving a data transmission comprising a plurality of packets at an edge port of the network, and routing the data transmission through the network with routing decisions based upon a routing table, wherein the routing table includes entries to effect routing decisions based upon a destination based hash function.
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Patent Agency Ranking
公开(公告)号：US12034633B2
公开(公告)日：2024-07-09
申请号：US17594745
申请日：2020-03-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Anthony Michael Ford , Timothy J. Johnson , Abdulla M. Bataineh
IPC: H04L45/28 , G06F9/50 , G06F9/54 , G06F12/0862 , G06F12/1036 , G06F12/1045 , G06F13/14 , G06F13/16 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/173 , H04L1/00 , H04L43/0876 , H04L43/10 , H04L45/00 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/12 , H04L45/122 , H04L45/125 , H04L45/16 , H04L45/24 , H04L45/42 , H04L45/745 , H04L45/7453 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/34 , H04L47/52 , H04L47/62 , H04L47/625 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/78 , H04L47/80 , H04L49/00 , H04L49/101 , H04L49/15 , H04L49/90 , H04L49/9005 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , H04L69/28
CPC classification number: H04L45/28 , G06F9/505 , G06F9/546 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F13/14 , G06F13/16 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F15/17331 , H04L1/0083 , H04L43/0876 , H04L43/10 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/122 , H04L45/123 , H04L45/125 , H04L45/16 , H04L45/20 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/42 , H04L45/46 , H04L45/566 , H04L45/70 , H04L45/745 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/18 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/323 , H04L47/34 , H04L47/39 , H04L47/52 , H04L47/621 , H04L47/6235 , H04L47/626 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/781 , H04L47/80 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/9005 , H04L49/9021 , H04L49/9036 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , G06F2212/50 , G06F2213/0026 , G06F2213/3808 , H04L69/28
Abstract: A data-driven intelligent networking system that can facilitate tracing of data flow packets is provided. The system add tracer packets to data flow packets arriving at an ingress point of the network. As the tracer packets progress through network in-band with the data flow packets, the system can copy, at each switch, trace data into pre-defined fields in the tracer packets. When the data flow packets arrive at an egress point of the network the system can separate the trace data from the data flow packet for analysis. Based on the analysis of the trace data, the system can adopt one or more policies to mitigate the impact of congestion on time-sensitive applications.
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公开(公告)号：US11968286B2
公开(公告)日：2024-04-23
申请号：US18142101
申请日：2023-05-02
Applicant: VIAVI SOLUTIONS INC.
Inventor： Sherwood Johnson
IPC: H04L69/22 , H04L45/745 , H04L49/00 , H04L49/90 , H04L49/9047
CPC classification number: H04L69/22 , H04L45/745 , H04L49/3018 , H04L49/9036 , H04L49/9047
Abstract: A packet filtering system uses linked zero-based binary search trees to filter received packets. The binary search trees may be generated from filter conditions defining filter parameters for filtering packets.
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8.发明公开公开(公告)号：US20240121180A1
公开(公告)日：2024-04-11
申请号：US18544791
申请日：2023-12-19
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Duncan Roweth , Andrew S. Kopser , Igor Gorodetsky , Laurence Scott Kaplan , Krishna Chaitanya Kandalla
IPC: H04L45/28 , G06F9/50 , G06F9/54 , G06F12/0862 , G06F12/1036 , G06F12/1045 , G06F13/14 , G06F13/16 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/173 , H04L1/00 , H04L43/0876 , H04L43/10 , H04L45/00 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/12 , H04L45/122 , H04L45/125 , H04L45/16 , H04L45/24 , H04L45/42 , H04L45/745 , H04L45/7453 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/34 , H04L47/52 , H04L47/62 , H04L47/625 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/78 , H04L47/80 , H04L49/00 , H04L49/101 , H04L49/15 , H04L49/90 , H04L49/9005 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40
CPC classification number: H04L45/28 , G06F9/505 , G06F9/546 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F13/14 , G06F13/16 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F15/17331 , H04L1/0083 , H04L43/0876 , H04L43/10 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/122 , H04L45/123 , H04L45/125 , H04L45/16 , H04L45/20 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/42 , H04L45/46 , H04L45/566 , H04L45/70 , H04L45/745 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/18 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/323 , H04L47/34 , H04L47/39 , H04L47/52 , H04L47/621 , H04L47/6235 , H04L47/626 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/781 , H04L47/80 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/9005 , H04L49/9021 , H04L49/9036 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , G06F2212/50 , G06F2213/0026 , G06F2213/3808 , H04L69/28
Abstract: A network interface controller (NIC) capable of efficient operation management for host accelerators is provided. The NIC can be equipped with a host interface and triggering logic block. During operation, the host interface can couple the NIC to a host device. The triggering logic block can obtain, via the host interface from the host device, an operation associated with an accelerator of the host device. The triggering logic block can determine whether a triggering condition has been satisfied for the operation based on an indicator received from the accelerator. If the triggering condition has been satisfied, the triggering logic block can obtain a piece of data generated from the accelerator from a memory location and execute the operation using the piece of data.
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公开(公告)号：US11916781B2
公开(公告)日：2024-02-27
申请号：US17594624
申请日：2020-03-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Partha Pratim Kundu , David Charles Hewson
IPC: H04L49/9005 , H04L49/90 , H04L49/9047 , G06F13/40 , H04L45/28 , H04L45/028 , H04L45/125 , H04L45/00 , H04L45/122 , H04L47/76 , H04L49/15 , H04L49/00 , H04L69/40 , H04L47/10 , H04L47/34 , H04L67/1097 , G06F13/16 , H04L45/021 , H04L47/12 , G06F13/42 , H04L47/2441 , H04L47/30 , H04L47/62 , H04L47/24 , G06F13/38 , H04L45/745 , H04L47/2483 , H04L47/629 , H04L47/80 , H04L49/101 , H04L45/12 , H04L47/122 , G06F12/1036 , G06F15/173 , H04L43/10 , H04L45/42 , H04L47/11 , G06F12/0862 , G06F12/1045 , H04L47/32 , G06F9/54 , G06F13/14 , G06F9/50 , H04L47/22 , H04L47/52 , H04L47/6275 , H04L45/24 , H04L45/7453 , H04L45/16 , H04L69/22 , H04L47/762 , H04L47/78 , H04L47/20 , H04L1/00 , H04L43/0876 , H04L47/2466 , H04L47/625 , H04L69/28
CPC classification number: H04L45/28 , G06F9/505 , G06F9/546 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F13/14 , G06F13/16 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F15/17331 , H04L1/0083 , H04L43/0876 , H04L43/10 , H04L45/021 , H04L45/028 , H04L45/122 , H04L45/123 , H04L45/125 , H04L45/16 , H04L45/20 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/42 , H04L45/46 , H04L45/566 , H04L45/70 , H04L45/745 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/18 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/323 , H04L47/34 , H04L47/39 , H04L47/52 , H04L47/621 , H04L47/626 , H04L47/629 , H04L47/6235 , H04L47/6275 , H04L47/76 , H04L47/762 , H04L47/781 , H04L47/80 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/9005 , H04L49/9021 , H04L49/9036 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , G06F2212/50 , G06F2213/0026 , G06F2213/3808 , H04L69/28
Abstract: A network interface controller (NIC) capable of efficiently utilizing an output buffer is provided. The NIC can be equipped with an output buffer, a host interface, an injector logic block, and an allocation logic block. The output buffer can include a plurality of cells, each of which can be a unit of storage in the output buffer. If the host interface receives a command from a host device, the injector logic block can generate a packet based on the command. The allocation logic block can then determine whether the packet is a multi-cell packet. If the packet is a multi-cell packet, the allocation logic block can determine a virtual index for the packet. The allocation logic block can then store, in an entry in a data structure, the virtual index, and a set of physical indices of cells storing the packet.
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公开(公告)号：US20240056385A1
公开(公告)日：2024-02-15
申请号：US18491879
申请日：2023-10-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Abdulla M. Bataineh , Jonathan Paul Beecroft , Thomas L. Court , Anthony M. Ford , Edwin L. Froese , David Charles Hewson , Joseph Kopnick , Andrew Kopser , Duncan Roweth , Gregory Faanes , Michael Higgins , Timothy J. Johnson , Trevor Jones , James Reinhard , Edward J. Turner , Steven L. Scott
IPC: H04L45/28 , H04L45/028 , H04L45/125 , H04L45/00 , H04L45/122 , H04L47/76 , H04L49/15 , H04L49/00 , H04L69/40 , H04L47/10 , H04L49/9005 , H04L47/34 , H04L67/1097 , G06F13/16 , H04L45/021 , H04L47/12 , G06F13/42 , H04L47/2441 , H04L47/30 , H04L47/62 , H04L47/24 , H04L49/90 , G06F13/38 , G06F13/40 , H04L45/745 , H04L47/2483 , H04L47/629 , H04L47/80 , H04L49/101 , H04L45/12 , H04L47/122 , G06F12/1036 , G06F15/173 , H04L43/10 , H04L45/42 , H04L47/11 , G06F12/0862 , G06F12/1045 , H04L47/32 , G06F9/54 , G06F13/14 , G06F9/50 , H04L47/22 , H04L47/52 , H04L47/6275 , H04L45/24 , H04L45/7453 , H04L45/16 , H04L69/22 , H04L47/762 , H04L47/78 , H04L47/20 , H04L49/9047 , H04L1/00 , H04L43/0876 , H04L47/2466 , H04L47/625
CPC classification number: H04L45/28 , H04L45/028 , H04L45/125 , H04L45/22 , H04L45/122 , H04L47/76 , H04L49/15 , H04L49/30 , H04L69/40 , H04L47/39 , H04L49/9005 , H04L47/34 , H04L67/1097 , G06F13/1673 , G06F13/1689 , H04L45/021 , H04L45/38 , H04L47/12 , G06F13/1642 , G06F13/4221 , H04L47/2441 , H04L47/30 , H04L47/621 , H04L47/24 , H04L49/9021 , G06F13/16 , G06F13/385 , G06F13/4022 , H04L45/745 , H04L47/2483 , H04L47/629 , H04L47/80 , H04L49/101 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L45/123 , H04L47/122 , H04L45/566 , G06F12/1036 , G06F15/17331 , H04L49/90 , H04L43/10 , H04L45/20 , H04L45/42 , H04L47/11 , H04L47/18 , G06F12/0862 , G06F12/1063 , H04L47/323 , G06F9/546 , G06F13/14 , G06F9/505 , H04L47/22 , H04L47/52 , H04L47/6275 , H04L45/24 , H04L45/7453 , H04L45/16 , H04L69/22 , G06F13/4068 , H04L47/6235 , H04L47/762 , H04L47/781 , H04L47/20 , H04L49/9036 , H04L49/9047 , H04L1/0083 , H04L43/0876 , H04L45/46 , H04L45/70 , H04L47/2466 , H04L47/626 , H04L47/32 , G06F2213/0026 , G06F2213/3808 , G06F2212/50 , H04L69/28
Abstract: A switch architecture for a data-driven intelligent networking system is provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.
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