Signal processing apparatus using a hierarchical neural network
    1.
    发明授权
    Signal processing apparatus using a hierarchical neural network 失效
    信号处理装置采用分层神经网络

    公开(公告)号:US5485548A

    公开(公告)日:1996-01-16

    申请号:US99719

    申请日:1993-07-29

    IPC分类号: G06N3/04 G06N3/063 G06F15/18

    CPC分类号: G06N3/063 G06N3/049

    摘要: In a neural network configured of neuron model cells, each neuron model cell is adapted to hold an input signal when a forward process is performed and to hold an error signal inputted when a learning process is performed. The signal processing apparatus is arranged to execute the forward process and the learning process in parallel.

    摘要翻译: 在由神经元模型单元配置的神经网络中,当执行前向处理时,每个神经元模型单元适于保持输入信号,并且在执行学习处理时保持输入的误差信号。 信号处理装置被配置为并行地执行前向处理和学习处理。

    Neuron unit and neuron unit network
    2.
    发明授权
    Neuron unit and neuron unit network 失效
    神经元单位和神经元单位网络

    公开(公告)号:US5324991A

    公开(公告)日:1994-06-28

    申请号:US989605

    申请日:1992-12-11

    IPC分类号: G06N3/063 G06F15/18

    CPC分类号: G06N3/063

    摘要: A neuron unit processes a plurality of binary input signals and outputs a neuron output signal which is indicative of a result of the processing. The neuron unit is provided with a plurality of first gates respectively for carrying out a logical operation on a binary input signal and a weighting coefficient, a second gate for carrying out a logical operation on an excitatory output signal of each of the first gates, a third gate for carrying out a logic operation on an inhibitory output signal of each of the first gates, a fourth gate for synthesizing output signals of the second and third gates and outputting the neuron output signal, and a generating circuit for generating the weighting coefficients which are supplied to each of the first gates. The generating circuit for generating one weighting coefficient includes a random number generator for generating random numbers, and a comparator for comparing each random number r with a predetermined value q and for outputting a pulse signal having first and second values depending on whether each random number r is such that r.ltoreq.q or r>q, and each weighting coefficient is described by a pulse density.

    摘要翻译: 神经元单元处理多个二进制输入信号并输出​​指示处理结果的神经元输出信号。 神经元单元分别设置有多个第一门,用于对二进制输入信号和加权系数进行逻辑运算,第二门用于对每个第一门的兴奋性输出信号进行逻辑运算, 第三门,用于对每个第一门的抑制输出信号进行逻辑运算,第四门,用于合成第二和第三门的输出信号并输出​​神经元输出信号;以及产生电路,用于产生加权系数, 被提供给每个第一门。 用于产生一个加权系数的产生电路包括用于产生随机数的随机数发生器和用于将每个随机数r与预定值q进行比较的比较器,并且用于根据每个随机数r是否输出具有第一和第二值的脉冲信号 是这样的,r = q或r> q,并且每​​个加权系数由脉冲密度来描述。

    Neuron unit
    3.
    发明授权
    Neuron unit 失效
    神经元单位

    公开(公告)号:US5327522A

    公开(公告)日:1994-07-05

    申请号:US989781

    申请日:1992-12-11

    IPC分类号: G06N3/063 G06F15/18

    CPC分类号: G06N3/063

    摘要: A neuron unit processes a plurality of input signals and for outputs an output signal which is indicative of a result of the processing, and includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a function generating part for generating new weight functions based on errors between the output signal of the forward process part and teaching signals and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part. The supplying part includes a memory for storing each weight function in the form of a binary value, and a generating circuit for generating a random pulse train based on each binary value stored in the memory. The random pulse train describes each weight function in the form of a pulse signal having a pulse density.

    摘要翻译: 神经元单元处理多个输入信号并输出​​表示处理结果的输出信号,并且包括用于接收输入信号的输入线,前向处理部分,包括用于提供加权函数的提供部分和操作 使用所述加权函数之一对所述输入信号执行操作并输出所述输出信号的部分,以及包括功能生成部分的自学习部分,用于基于所述输入信号的输出信号之间的误差生成新的加权函数 前向处理部分和教学信号,以及变化部分,用于将由前向处理部分的供给部分提供的权重函数改变为由生成部分生成的新的权重函数。 供给部分包括用于以二进制值的形式存储每个加权函数的存储器,以及用于基于存储在存储器中的每个二进制值产生随机脉冲串的产生电路。 随机脉冲串以具有脉冲密度的脉冲信号的形式描述每个权重函数。