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    System signaling schemes for processor and memory module
    1.
    发明授权
    System signaling schemes for processor and memory module 失效
    用于处理器和存储器模块的系统信令方案

    公开(公告)号：US06185704B2

    公开(公告)日：2001-02-06

    申请号：US09058000

    申请日：1998-04-09

    申请人： Basavaraj I. Pawate ,  Matthew A. Woolsey ,  Douglas L. Mahlum ,  Fred J. Reuter ,  Yoshihide Iwata ,  Judd E. Heape

    发明人： Basavaraj I. Pawate ,  Matthew A. Woolsey ,  Douglas L. Mahlum ,  Fred J. Reuter ,  Yoshihide Iwata ,  Judd E. Heape

    IPC分类号： G11C2900

    CPC分类号： G06F12/0684 ,  G11C5/04

    摘要： A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and digital signal processor circuitry (44) including one or more digital signal processors (56). The DSP/memory module (40) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor (56) performs operations on data for retrieval by the main processing unit (12).

    摘要翻译： 计算机系统包括耦合到DSP /存储器模块（40）的主处理单元（12）。 DSP /存储器模块（40）包括半导体存储器（42）和包括一个或多个数字信号处理器（56）的数字信号处理器电路（44）。 DSP /存储器模块（40）可以被放置在诸如SIMM或DIMM插槽的标准主存储器插槽中，并且被用作传统的主存储器。 存储器模块也可以以智能模式使用，其中数字信号处理器（56）对由主处理单元（12）检索的数据执行操作。

    Apparatus and method for a memory unit with a processor integrated therein
    4.
    发明授权
    Apparatus and method for a memory unit with a processor integrated therein 失效
    一种具有集成在其中的处理器的存储器单元的装置和方法

    公开(公告)号：US5678021A

    公开(公告)日：1997-10-14

    申请号：US324291

    申请日：1994-10-17

    申请人： Basavaraj I. Pawate ,  Kenneth A. Poteet ,  Joe H. Neal

    发明人： Basavaraj I. Pawate ,  Kenneth A. Poteet ,  Joe H. Neal

    IPC分类号： G06F15/78 ,  G06F13/16 ,  G06F12/00

    CPC分类号： G06F15/7821

    摘要： A smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard memory device. In a first mode of operation, the smart memory (10) is a data storage facility for an associated central processing unit (22). In a second mode of operation, the smart memory (10) is a storage facility for the processing core (14 and 16) and for central processing unit (22) for simultaneous execution of instructions. The central processing unit (22) controls the mode of operation and determines the instructions executed by the processing core (14 and 16). The wide data bus, available with an integrated processor/storage facility, permits certain processing operations to be off-loaded to the smart memory (10) where the processing operations can be performed more efficiently.

    摘要翻译： 提供了一种智能存储器（10），其包括用于执行存储在数据存储区域（12和18）中的指令的数据存储器（12和18）和处理核心（14和16）。 在外部，智能存储器（10）可以作为标准存储器件直接访问。 在第一操作模式中，智能存储器（10）是用于相关联的中央处理单元（22）的数据存储设备。 在第二操作模式中，智能存储器（10）是用于处理核心（14和16）和中央处理单元（22）的用于同时执行指令的存储设备。 中央处理单元（22）控制操作模式并确定由处理核心（14和16）执行的指令。 具有集成处理器/存储设施的宽数据总线允许某些处理操作被卸载到智能存储器（10），其中可以更有效地执行处理操作。

    System signalling schemes for processor & memory module
    5.
    发明授权
    System signalling schemes for processor & memory module 有权
    处理器和内存模块的系统信令方案

    公开(公告)号：US06584588B1

    公开(公告)日：2003-06-24

    申请号：US09698089

    申请日：2000-10-30

    申请人： Basavaraj I. Pawate ,  Matthew A. Woolsey ,  Douglas L. Mahlum ,  Fred J. Reuter ,  Yoshihide Iwata ,  Judd E. Heape

    发明人： Basavaraj I. Pawate ,  Matthew A. Woolsey ,  Douglas L. Mahlum ,  Fred J. Reuter ,  Yoshihide Iwata ,  Judd E. Heape

    IPC分类号： G11C2900

    CPC分类号： G06F12/0684 ,  G11C5/04

    摘要： A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and digital signal processor circuitry (44) including one or more digital signal processors (56). The DSP/memory module (40) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor (56) performs operations on data for retrieval by the main processing unit (12).

    摘要翻译： 计算机系统包括耦合到DSP /存储器模块（40）的主处理单元（12）。 DSP /存储器模块（40）包括半导体存储器（42）和包括一个或多个数字信号处理器（56）的数字信号处理器电路（44）。 DSP /存储器模块（40）可以被放置在诸如SIMM或DIMM插槽的标准主存储器插槽中，并且被用作传统的主存储器。 存储器模块也可以以智能模式使用，其中数字信号处理器（56）对由主处理单元（12）检索的数据执行操作。

    Direct memory access scheme using memory with an integrated processor having communication with external devices
    7.
    发明授权
    Direct memory access scheme using memory with an integrated processor having communication with external devices 失效
    使用具有与外部设备通信的集成处理器的存储器的直接存储器访问方案

    公开(公告)号：US5638530A

    公开(公告)日：1997-06-10

    申请号：US49909

    申请日：1993-04-20

    申请人： Basavaraj I. Pawate ,  Gene A. Frantz ,  Rajan Chirayil

    发明人： Basavaraj I. Pawate ,  Gene A. Frantz ,  Rajan Chirayil

    IPC分类号： G06F13/28 ,  G06F15/78 ,  G06F12/00

    CPC分类号： G06F13/28 ,  G06F15/7842

    摘要： A method and system are provided for improved processing between a host computer (200) and process logic (170). Data instructions are stored at multiple memory locations of a memory (150). The data are processed in response to instructions by the process logic (170), which is integrated with the memory (150) within a single integrated circuit. The memory locations are directly accessible without bus arbitration by the external device coupled to the single integrated circuit through an external interface (180), which controls the processing speed of the process logic (170).

    摘要翻译： 提供了一种方法和系统，用于改善主计算机（200）和处理逻辑（170）之间的处理。 数据指令存储在存储器（150）的多个存储器位置。 响应于在单个集成电路内与存储器（150）集成的处理逻辑（170）的指令来处理数据。 存储器位置可以通过外部设备直接访问，而外部设备通过控制处理逻辑（170）的处理速度的外部接口（180）耦合到单个集成电路。

    Method and system for time scale modification utilizing feature vectors about zero crossing points
    8.
    发明授权
    Method and system for time scale modification utilizing feature vectors about zero crossing points 失效
    利用关于零交叉点的特征向量进行时间尺度修正的方法和系统

    公开(公告)号：US5749064A

    公开(公告)日：1998-05-05

    申请号：US609335

    申请日：1996-03-01

    申请人： Basavaraj I. Pawate ,  Susan Yim

    发明人： Basavaraj I. Pawate ,  Susan Yim

    IPC分类号： G10H1/36 ,  G10K15/04 ,  G10L21/04 ,  G10L3/02 ,  G10L9/12

    CPC分类号： G10H1/366 ,  G10L21/04 ,  G10H2250/035

    摘要： A method and system for implementing time scale modification wherein the method includes a Zero Crossing Module (22) for determining zero crossing points in the signal, a Feature Vector Module (24) for generating feature vectors describing the zero crossing points, a Distance Metric Module (26) for generating distance metrics describing local characteristics at the zero crossing points, an Alignment Module (28) for using the feature vectors and distance metrics for aligning and synchronizing the signal in accordance with local similarities and similarity over a selected time interval to generate a time scale modified signal. The present invention also includes a Cross Fade Module (20) for smoothing transitions between successive frames of the resulting time scale modified signal.

    摘要翻译： 一种用于实现时间尺度修改的方法和系统，其中所述方法包括用于确定所述信号中的过零点的零交叉模块（22），用于生成描述过零点的特征向量的特征向量模块（24），距离度量模块 （26），用于产生描绘过零点处的局部特性的距离度量;对准模块（28），用于使用所述特征向量和距离度量来根据所选时间间隔上的局部相似性和相似性来对齐和同步所述信号，以产生 时间尺度修改信号。 本发明还包括用于平滑所产生的时标修改信号的连续帧之间的转换的交叉衰落模块（20）。

    Apparatus and method for identifying a speech pattern
    9.
    发明授权
    Apparatus and method for identifying a speech pattern 失效
    用于识别语音图案的装置和方法

    公开(公告)号：US5222190A

    公开(公告)日：1993-06-22

    申请号：US713481

    申请日：1991-06-11

    申请人： Basavaraj I. Pawate ,  George R. Doddington

    发明人： Basavaraj I. Pawate ,  George R. Doddington

    IPC分类号： G10L15/04 ,  G10L11/02 ,  G10L15/00 ,  G10L15/10

    CPC分类号： G10L25/87

    摘要： A method and apparatus are provided for identifying one or more boundaries of a speech pattern within an input utterance. One or more anchor patterns are defined, and an input utterance is received. An anchor section of the input utterance is identified as corresponding to at least one of the anchor patterns. A boundary of the speech pattern is defined based upon the anchor section. Also provided are a method and apparatus for identifying a speech pattern within an input utterance. One or more segment patterns are defined, and an input utterance is received. Portions of the input utterance which correspond to the segment patterns are identified. One or more of the segments of the input utterance are defined responsive to the identified portions.

    Efficient pruning algorithm for hidden markov model speech recognition
    10.
    发明授权
    Efficient pruning algorithm for hidden markov model speech recognition 失效
    隐马尔可夫模型语音识别的有效修剪算法

    公开(公告)号：US4977598A

    公开(公告)日：1990-12-11

    申请号：US337608

    申请日：1989-04-13

    申请人： George R. Doddington ,  Basavaraj I. Pawate

    发明人： George R. Doddington ,  Basavaraj I. Pawate

    IPC分类号： G06F3/16 ,  G10L11/00 ,  G10L15/14

    CPC分类号： G10L15/14

    摘要： An efficient pruning method reduces central processing unit (CPU) loading during real time speech recognition by instructing the CPU to compare a current state's previously calculated probability score against a predetermined threshold value and to discard hypothesis containing states with probability scores below such threshold. After determining that the current state should be kept, the CPU is directed to locate an available slot in the scoring buffer where information about the current state is then stored. The CPU locates an available slot by comparing the current time-index with the time-index associated with each scoring buffer slot. When they are equal, the slot is considered not available; when the current time-index is greater, the slot is considered available. After the information about the current state is stored, the CPU then sets the current state's backpointer to point at the start state of the current best path if the current states represents a completed model. Regardless of the current state's status, the CPU then associates the current time-index with the time-indices of all the slots along the best path to the current state. The CPU then proceeds to calculate the probability score of the next current state and the method repeats until all states have been completed.