公开(公告)号：US4156287A

公开(公告)日：1979-05-22

申请号：US881434

申请日：1978-02-27

Applicant: Satish L. Rege ,  Beng-Yu Woo

Inventor： Satish L. Rege ,  Beng-Yu Woo

IPC: G11C19/28 ,  G11C21/00

CPC classification number: G11C19/287 ,  G11C19/285

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

公开(公告)号：US4112504A

公开(公告)日：1978-09-05

申请号：US734351

申请日：1976-10-20

Applicant: Satish L. Rege ,  Beng-Yu Woo

Inventor： Satish L. Rege ,  Beng-Yu Woo

IPC: G11C19/28 ,  G11C21/00

CPC classification number: G11C19/287 ,  G11C19/285

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract translation: 本公开涉及具有并行环路或轨道的快速存取CCD存储器组合，其中可以存储在单个计算器芯片上的数据位的总数取决于由多个刷新放大器组成的开销电路和切换所需的各种开关 从存储轨道到读/写位置的存储数据以及刷新放大器的数量以及将时钟脉冲分配到各个存储轨道所需的控制电路。 随着开关和刷新放大器的数量增加，存储位所需的总面积也增加。 随着时钟开关的数量增加，半导体芯片的功耗降低。 随着刷新放大器的数量增加，访问时间和总服务时间减少。 公开了许多不同的最佳记忆组织。

公开(公告)号：US4215423A

公开(公告)日：1980-07-29

申请号：US947556

申请日：1978-10-02

Applicant: Satish L. Rege ,  Beng-Yu Woo

Inventor： Satish L. Rege ,  Beng-Yu Woo

IPC: G11C19/28 ,  G11C21/00

CPC classification number: G11C19/287 ,  G11C19/285

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract translation: 本公开涉及具有并行环路或轨道的快速存取CCD存储器组合，其中可以存储在单个计算器芯片上的数据位的总数取决于由多个刷新放大器组成的开销电路和切换所需的各种开关 从存储轨道到读/写位置的存储数据以及刷新放大器的数量以及将时钟脉冲分配到各个存储轨道所需的控制电路。 随着开关和刷新放大器的数量增加，存储位所需的总面积也增加。 随着时钟开关的数量增加，半导体芯片的功耗降低。 随着刷新放大器的数量增加，访问时间和总服务时间减少。 公开了许多不同的最佳记忆组织。

公开(公告)号：US5781788A

公开(公告)日：1998-07-14

申请号：US939997

申请日：1997-09-29

Applicant: Beng-Yu Woo ,  Xiaoming Li ,  Vivian Hsiun

Inventor： Beng-Yu Woo ,  Xiaoming Li ,  Vivian Hsiun

IPC: G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  G06F13/00

CPC classification number: H04N19/423 ,  H04N19/42 ,  H04N19/61

Abstract: A single-chip video compression/decompression (video codec) chip is connected to receive a video input from a NTSC-compatible or PAL-compatible camera and a transmit channel. Video information from the camera or other video input source is compressed by the video codec and transmitted out in compressed form on a transmit channel. Concurrently, compressed video information is input to the video codec from a receive channel, decompressed and output to the monitor or other video output device, e.g., a television set. Only a separate single module of dynamic random access memory (DRAM) is needed to provide storage for incoming and outgoing video data, compressed bit streams and reconstructed pictures for both compression and decompression procedures. The compression of video information is by spatial decorrelation of the intraframe information, and temporal decorrelation of the interframe information. The communication channel bit rate is further reduced by quantization and variable length coding. Intraframe coding uses the redundancy of information within a single frame. The processing is done on blocks of eight-by-eight pixels. Both the luminance and chrominance pixel blocks are transform coded by a discrete cosine transform that changes the pixels from spatial domain to frequency domain.

Abstract translation: 连接单芯片视频压缩/解压缩（视频编解码器）芯片以从NTSC兼容或PAL兼容的摄像机和发送信道接收视频输入。 来自相机或其他视频输入源的视频信息被视频编解码器压缩，并以压缩形式在发送信道上发送出去。 同时，压缩视频信息从接收通道输入到视频编解码器，解压缩并输出到监视器或其他视频输出设备，例如电视机。 仅需要单独的动态随机存取存储器单元（DRAM）来为压缩和解压缩过程的输入和输出视频数据，压缩比特流和重构图像提供存储。 视频信息的压缩是通过帧内信息的空间去相关，以及帧间信息的时间去相关。 通过量化和可变长度编码进一步减少通信信道比特率。 帧内编码使用单个帧内信息的冗余。 处理是在8×8像素的块上完成的。 亮度和色度像素块都通过将像素从空间域改变到频域的离散余弦变换进行变换编码。