利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.037 seconds)

    SIMD supporting filtering in a video decoding system
    2.
    发明授权
    SIMD supporting filtering in a video decoding system 有权
    SIMD支持在视频解码系统中进行滤波

    公开(公告)号：US08516026B2

    公开(公告)日：2013-08-20

    申请号：US10786195

    申请日：2004-02-25

    Applicant: Alexander G. MacInnis ,  Vivian Hsiun

    Inventor： Alexander G. MacInnis ,  Vivian Hsiun

    IPC: G06F17/10

    CPC classification number: H04N19/42 ,  H03H17/02 ,  H04N19/80

    Abstract: A filter engine that performs filtering operations on an input data stream comprising blocks of data. The filter engine includes a first memory element, a second memory element, a first shift register, a second shift register and a processor. The first and second memory elements store blocks of data to be processed. The first shift register receives and stores blocks of data from the first memory element. The second shift register receives and stores blocks of data from the second memory element. The first and second shift registers are adapted to selectively shift their contents by a predetermined number of bits corresponding to the size of a data element, such as a pixel. The processor receives blocks of data from the first and second shift registers and simultaneously performs filtering operations on blocks of data from the first and second shift registers.

    Abstract translation: 对包括数据块的输入数据流执行滤波操作的滤波器引擎。 滤波器引擎包括第一存储器元件，第二存储器元件，第一移位寄存器，第二移位寄存器和处理器。 第一和第二存储器元件存储要处理的数据块。 第一移位寄存器接收并存储来自第一存储器元件的数据块。 第二移位寄存器接收并存储来自第二存储元件的数据块。 第一和第二移位寄存器适于选择性地将它们的内容移位与数据元素（诸如像素）的大小相对应的预定数量的位。 处理器从第一移位寄存器和第二移位寄存器接收数据块，同时对来自第一移位寄存器和第二移位寄存器的数据块执行滤波操作。

    Video decoding system supporting multiple standards
    3.
    发明授权
    Video decoding system supporting multiple standards 有权
    视频解码系统支持多种标准

    公开(公告)号：US07881385B2

    公开(公告)日：2011-02-01

    申请号：US11015555

    申请日：2004-12-17

    Applicant: Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    Inventor： Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    IPC: H04N7/18

    CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

    Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

    Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。

    Video decoding system supporting multiple standards
    5.
    发明申请
    Video decoding system supporting multiple standards 有权
    视频解码系统支持多种标准

    公开(公告)号：US20050123057A1

    公开(公告)日：2005-06-09

    申请号：US11015555

    申请日：2004-12-17

    Applicant: Alexander MacInnis ,  Jose' Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    Inventor： Alexander MacInnis ,  Jose' Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    IPC: G06F9/38 ,  G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N7/12

    CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

    Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

    Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。

    Full duplex single clip video codec
    7.
    发明授权
    Full duplex single clip video codec 失效
    全双工单芯片视频编解码器

    公开(公告)号：US5781788A

    公开(公告)日：1998-07-14

    申请号：US939997

    申请日：1997-09-29

    Applicant: Beng-Yu Woo ,  Xiaoming Li ,  Vivian Hsiun

    Inventor： Beng-Yu Woo ,  Xiaoming Li ,  Vivian Hsiun

    IPC: G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  G06F13/00

    CPC classification number: H04N19/423 ,  H04N19/42 ,  H04N19/61

    Abstract: A single-chip video compression/decompression (video codec) chip is connected to receive a video input from a NTSC-compatible or PAL-compatible camera and a transmit channel. Video information from the camera or other video input source is compressed by the video codec and transmitted out in compressed form on a transmit channel. Concurrently, compressed video information is input to the video codec from a receive channel, decompressed and output to the monitor or other video output device, e.g., a television set. Only a separate single module of dynamic random access memory (DRAM) is needed to provide storage for incoming and outgoing video data, compressed bit streams and reconstructed pictures for both compression and decompression procedures. The compression of video information is by spatial decorrelation of the intraframe information, and temporal decorrelation of the interframe information. The communication channel bit rate is further reduced by quantization and variable length coding. Intraframe coding uses the redundancy of information within a single frame. The processing is done on blocks of eight-by-eight pixels. Both the luminance and chrominance pixel blocks are transform coded by a discrete cosine transform that changes the pixels from spatial domain to frequency domain.

    Abstract translation: 连接单芯片视频压缩/解压缩（视频编解码器）芯片以从NTSC兼容或PAL兼容的摄像机和发送信道接收视频输入。 来自相机或其他视频输入源的视频信息被视频编解码器压缩，并以压缩形式在发送信道上发送出去。 同时，压缩视频信息从接收通道输入到视频编解码器，解压缩并输出到监视器或其他视频输出设备，例如电视机。 仅需要单独的动态随机存取存储器单元（DRAM）来为压缩和解压缩过程的输入和输出视频数据，压缩比特流和重构图像提供存储。 视频信息的压缩是通过帧内信息的空间去相关，以及帧间信息的时间去相关。 通过量化和可变长度编码进一步减少通信信道比特率。 帧内编码使用单个帧内信息的冗余。 处理是在8×8像素的块上完成的。 亮度和色度像素块都通过将像素从空间域改变到频域的离散余弦变换进行变换编码。

    Method of operating a video decoding system
    10.
    发明授权
    Method of operating a video decoding system 有权
    操作视频解码系统的方法

    公开(公告)号：US08005147B2

    公开(公告)日：2011-08-23

    申请号：US11400949

    申请日：2006-04-05

    Applicant: Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    Inventor： Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

    IPC: H04N7/18

    CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

    Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

    Abstract translation: 一种用于解码数字视频数据流的系统和方法。 在一个方面，多个硬件加速模块与核心处理器一起使用。 加速器在解码管线中操作，其中在任何给定阶段，每个加速器对视频数据的特定宏块进行操作。 在随后的流水线阶段，每个加速器对数据流中的下一个宏块进行工作，该前一阶段的另一个加速器工作。 核心处理器在每个阶段轮询所有加速器。 当所有加速器在给定阶​​段完成任务时，核心处理器启动下一阶段。 在另一方面，采用两个可变长度解码器来同时解码视频帧的两个宏块行。 每个可变长度解码器用于对分配的行进行解码，并行并行地进行可变长度解码。 可变长度解码器作为流水线的一部分进行操作，其中可变长度解码器逐级交替解码宏块。

Patent Agency Ranking