公开(公告)号：US08022917B2

公开(公告)日：2011-09-20

申请号：US11439278

申请日：2006-05-24

申请人： Kun-Tsung Lin ,  Kuei-Kai Chang ,  Bo-Wen Wang

发明人： Kun-Tsung Lin ,  Kuei-Kai Chang ,  Bo-Wen Wang

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3655 ,  G09G2320/0233 ,  G09G2330/023

摘要： An LCD panel driving method and device with charge sharing is disclosed. The LCD panel includes a plurality of switches, a plurality of data lines, a signal driving circuit for generating a plurality of image signals, a charge sharing common voltage driving circuit and a common capacitor having one end connected to the charge sharing common voltage driving circuit through a common voltage node. The method turns the switches on to thereby form the charge sharing common voltage driving circuit and the signal driving circuit as a short circuit, such that charges stored in the common capacitor flow into the data lines to drive the common voltage node to enter in an inverse phase state in order to sequentially turn the switches on and then off to accordingly sample the respective data lines.

摘要翻译： 公开了一种具有电荷共享的LCD面板驱动方法和装置。 LCD面板包括多个开关，多个数据线，用于产生多个图像信号的信号驱动电路，电荷共享公共电压驱动电路和公共电容器，其一端连接到电荷共用公共电压驱动电路 通过公共电压节点。 该方法使开关接通，从而形成电荷共用公共电压驱动电路和信号驱动电路作为短路，使得存储在公共电容器中的电荷流入数据线，驱动公共电压节点进入反向 相位状态，以顺序地打开开关，然后关闭，从而相应地对各个数据线进行采样。

公开(公告)号：US06552708B1

公开(公告)日：2003-04-22

申请号：US09657259

申请日：2000-09-07

申请人： Bo-Wen Wang ,  Jun-Ren Shih ,  Shang-Li Chen

发明人： Bo-Wen Wang ,  Jun-Ren Shih ,  Shang-Li Chen

IPC分类号： G04G336

CPC分类号： G09G3/2011 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2310/0291 ,  H03F3/505

摘要： The present invention is related to a unit gain buffer of the driver circuit to drive the data line in the filed of LCD data driver, further to be preferably applied to the new TFT-LCD processing of low temperature poly-silicon. This invention is using the plurality of PMOS transistor connection to result in the almost same value between the Vout and Vin. There is no using of the feedback connection in this invention, so the using of the compensation capacitor can be avoided, furthermore the data driver layout area of the LCD driver can be reduced. This invention can improve the defect of the larger layout area result from the prior art.

摘要翻译： 本发明涉及用于驱动LCD数据驱动器领域的数据线的驱动电路的单位增益缓冲器，进一步优选地应用于低温多晶硅的新TFT-LCD处理。 本发明使用多个PMOS晶体管连接导致Vout和Vin之间几乎相同的值。 在本发明中没有使用反馈连接，因此可以避免使用补偿电容器，此外可以降低LCD驱动器的数据驱动器布局面积。 本发明可以改善现有技术中较大布局区域结果的缺陷。

公开(公告)号：US06467057B1

公开(公告)日：2002-10-15

申请号：US09516534

申请日：2000-03-01

申请人： Bo-Wen Wang ,  Shang-Li Chen

发明人： Bo-Wen Wang ,  Shang-Li Chen

IPC分类号： H04B1700

CPC分类号： G09G3/3677 ,  G09G2330/08

摘要： A scan driver of LCD with fault detection and correction circuit is disclosed herein. The scan driver fabricated on a glass substrate locates at both ends of the scan buses can simultaneously drive the scan buses from both ends. The fault detection and correction circuit of the scan driver is used to determine whether transmitting signal from a DFF at present stage into a DFF at next stage, or transmitting signal from the other DFF at present stage through a scan bus into the other DFF. The fault detection and correction circuit includes the first detecting device, the second detecting device, the control signal generating device, and the transmission control device. The first and the second detecting device generate a first logic level and a second logic level responding to a stuck-at-zero fault and a stuck-at-one fault respectively. The control signal generating device generates a first control signal when all input terminals exhibiting a second logic level, and generates a second control signal when one of input terminals exhibiting the first logic level. The transmission control device can transmit signal from one DFF to the other and to the scan bus responding to the first control signal, also can isolate them and the scan bus responding to the second control signal.

摘要翻译： 本文公开了具有故障检测和校正电路的LCD的扫描驱动器。 位于扫描总线两端的位于玻璃基板上的扫描驱动器可以同时从两端驱动扫描总线。 扫描驱动器的故障检测和校正电路用于确定在现阶段从DFF发送信号到下一级的DFF，还是将来自其他DFF的信号通过扫描总线传输到另一个DFF。 故障检测和校正电路包括第一检测装置，第二检测装置，控制信号产生装置和传输控制装置。 第一和第二检测装置分别产生第一逻辑电平和第二逻辑电平，其响应于卡住在零故障和卡住在一个故障。 当所有输入端呈现第二逻辑电平时，控制信号产生装置产生第一控制信号，并且当呈现第一逻辑电平的输入端之一产生第二控制信号。 发送控制装置可以根据第一控制信号将信号从一个DFF发送到另一个发送信号和扫描总线，也可以隔离它们和扫描总线响应第二个控制信号。

公开(公告)号：US06829322B2

公开(公告)日：2004-12-07

申请号：US10617782

申请日：2003-07-14

申请人： Jun-Ren Shih ,  Shang-Li Chen ,  Bo-Wen Wang ,  Jan-Ruei Lin

发明人： Jun-Ren Shih ,  Shang-Li Chen ,  Bo-Wen Wang ,  Jan-Ruei Lin

IPC分类号： G11C1900

CPC分类号： G11C19/00 ,  G11C19/28

摘要： A shift-register unit. The first transistor includes a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal. The second transistor includes a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to initial the shift-register unit. The third transistor includes a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal. The fourth transistor includes a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.

摘要翻译： 移位寄存器单元。 第一晶体管包括耦合到第一端子的第一源极/漏极，第二源极/漏极以及耦合到复位信号的第一栅极，以停止移位寄存器单元输出脉冲信号。 第二晶体管包括耦合到第二源极/漏极的第三源极/漏极，耦合到第二端子的第四源极/漏极和耦合到设置信号的第二栅极以初始化移位寄存器单元。 第三晶体管包括耦合到输出端的第五源极/漏极，耦合到第二源极/漏极的第三栅极和耦合到时钟信号的第六源极/漏极，以开始输出脉冲信号。 第四晶体管包括耦合到第一端子的第七源极/漏极，耦合到输出端子的第八源极/漏极和耦合到刷新信号的第四栅极，以将待机模式中的移位寄存器单元的电压电平设置。