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1.发明授权Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device 有权用于测试FPGA器件中可配置互连网络的可扩展和并行处理方法和结构公开(公告)号：US06725442B1
公开(公告)日：2004-04-20
申请号：US10235380
申请日：2002-09-04
IPC分类号： G06F1750
CPC分类号： G01R31/318519
摘要： Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states. At least one of the stepped-into states is sensed and analyzed after a predefined number of steps have been taken in order to determine whether the detected state matches the expected state for the predefined number of steps. If it does not, that is taken to indicate that a defect exists in the under-test FPGA. Plural sequential state machines can be exercised in parallel within a given FPGA so that large numbers of interconnect resources can be simultaneously challenged.
摘要翻译： 现场可编程门阵列（FPGA）的可配置互连资源通过配置至少一些查找表（LUT），寄存器和输入信号获取器来测试，以实现一个或多个顺序状态机，其通过至少一些 互连导体连接到LUT的输入端。 反馈信号由LUT解码，用于定义一个或多个顺序状态机的下一状态。 每个顺序状态机可以被编程为顺序地步进许多独特的状态，其中独特状态挑战互连导体的能力来切换不同信号电平的组合。 顺序状态机被执行以顺序地通过其独特状态中的多个状态。 在已经采取预定数量的步骤之后感测和分析至少一个步进状态，以便确定检测到的状态是否与预定数量的步骤的预期状态相匹配。 如果没有，则表示在测试中的FPGA中存在缺陷。 多个顺序状态机可以在给定的FPGA中并行运行，从而可以同时挑战大量互连资源。
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2.发明授权Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device 失效用于测试FPGA器件中可配置互连网络的可扩展和并行处理方法和结构公开(公告)号：US06470485B1
公开(公告)日：2002-10-22
申请号：US09692694
申请日：2000-10-18
IPC分类号： H03K17693
CPC分类号： G01R31/318519
摘要： Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states. At least one of the stepped-into states is sensed and analyzed after a predefined number of steps have been taken in order to determine whether the detected state matches the expected state for the predefined number of steps. If it does not, that is taken to indicate that a defect exists in the under-test FPGA. Plural sequential state machines can be exercised in parallel within a given FPGA so that large numbers of interconnect resources can be simultaneously challenged.
摘要翻译： 现场可编程门阵列（FPGA）的可配置互连资源通过配置至少一些查找表（LUT），寄存器和输入信号获取器来测试，以实现一个或多个顺序状态机，其通过至少一些 互连导体连接到LUT的输入端。 反馈信号由LUT解码，用于定义一个或多个顺序状态机的下一状态。 每个顺序状态机可以被编程为顺序地步进许多独特的状态，其中独特状态挑战互连导体的能力来切换不同信号电平的组合。 顺序状态机被执行以顺序地通过其独特状态中的多个状态。 在已经采取预定数量的步骤之后感测和分析至少一个步进状态，以便确定检测到的状态是否与预定数量的步骤的预期状态相匹配。 如果没有，则表示在测试中的FPGA中存在缺陷。 多个顺序状态机可以在给定的FPGA中并行运行，从而可以同时挑战大量互连资源。
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