公开(公告)号：US06470485B1

公开(公告)日：2002-10-22

申请号：US09692694

申请日：2000-10-18

申请人： Richard T. Cote ,  Brenda Nguyen ,  Xuan D. Pham ,  Bradley A. Sharpe-Geisler

发明人： Richard T. Cote ,  Brenda Nguyen ,  Xuan D. Pham ,  Bradley A. Sharpe-Geisler

IPC分类号： H03K17693

CPC分类号： G01R31/318519

摘要： Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states. At least one of the stepped-into states is sensed and analyzed after a predefined number of steps have been taken in order to determine whether the detected state matches the expected state for the predefined number of steps. If it does not, that is taken to indicate that a defect exists in the under-test FPGA. Plural sequential state machines can be exercised in parallel within a given FPGA so that large numbers of interconnect resources can be simultaneously challenged.

摘要翻译： 现场可编程门阵列（FPGA）的可配置互连资源通过配置至少一些查找表（LUT），寄存器和输入信号获取器来测试，以实现一个或多个顺序状态机，其通过至少一些 互连导体连接到LUT的输入端。 反馈信号由LUT解码，用于定义一个或多个顺序状态机的下一状态。 每个顺序状态机可以被编程为顺序地步进许多独特的状态，其中独特状态挑战互连导体的能力来切换不同信号电平的组合。 顺序状态机被执行以顺序地通过其独特状态中的多个状态。 在已经采取预定数量的步骤之后感测和分析至少一个步进状态，以便确定检测到的状态是否与预定数量的步骤的预期状态相匹配。 如果没有，则表示在测试中的FPGA中存在缺陷。 多个顺序状态机可以在给定的FPGA中并行运行，从而可以同时挑战大量互连资源。

公开(公告)号：US06737958B1

公开(公告)日：2004-05-18

申请号：US09714706

申请日：2000-11-16

申请人： Srinagesh Satyanarayana

发明人： Srinagesh Satyanarayana

IPC分类号： H03K17693

CPC分类号： H03K17/6228 ,  H03K17/6235

摘要： A crosspoint switch architecture implements high-speed packet switches and incorporates a power-saving bias control circuit with each switch cell. Each switch cell is equipped with two memory cells and a bias control circuit. Power savings are obtained by controlling the bias current of the switch cell as a function of the switch state. Although the additional circuitry accompanying each switch cell adds complexity and a minimal additional power consumption, the power saving realized in the switch cell results in a crosspoint switch with much lower power consumption as compared to existing architectures. The presence of two bits of memory for each switch core allows for fast reconfiguration. The result is an overall power savings and lower cost design.

摘要翻译： 交叉点交换架构实现高速分组交换，并且与每个交换机单元并入节能偏置控制电路。 每个开关单元配备有两个存储单元和偏置控制电路。 通过控制开关单元的偏置电流作为开关状态的函数来获得功率节省。 虽然伴随每个开关单元的附加电路增加了复杂性和最小的附加功耗，但与现有架构相比，在开关单元中实现的功率节省导致交叉点开关具有低得多的功耗。 每个交换机内核存在两位内存，可以快速重新配置。 其结果是整体节电和降低成本设计。

公开(公告)号：US06791479B2

公开(公告)日：2004-09-14

申请号：US09821977

申请日：2001-03-30

申请人： Richard Alen Kraus ,  Charles Thomas Clark

发明人： Richard Alen Kraus ,  Charles Thomas Clark

IPC分类号： H03K17693

CPC分类号： G01R31/318533 ,  G01R31/3004

摘要： A logic state detection system for detecting the state of at least one state changing device includes a scanning circuit and a current detection circuit. The scanning circuit selectively activates at least one output line electrically connected with the at least one state changing device. Current passes through the scanning circuit to the at least one output line that is activated. The current detection circuit determines whether the state changing device is in a conducting or a non-conducting state as a function of the current.

摘要翻译： 用于检测至少一个状态改变装置的状态的逻辑状态检测系统包括扫描电路和电流检测电路。 扫描电路选择性地激活与至少一个状态改变装置电连接的至少一个输出线。 电流通过扫描电路到被激活的至少一个输出线。 电流检测电路根据电流确定状态改变装置是导通状态还是非导通状态。

公开(公告)号：US06314551B1

公开(公告)日：2001-11-06

申请号：US09102465

申请日：1998-06-22

申请人： David J. Borland

发明人： David J. Borland

IPC分类号： H03K17693

CPC分类号： G06F15/7867

摘要： An integrated circuit including a main system processing unit which can be extended using a plurality of programmable logic unit for a plurality of possible functions, and a system for programming same. The integrated circuit also includes a plurality of functional logic blocks, a plurality of input/output (I/O) pads, and programmable logic coupled to each of the plurality of functional logic blocks. The main system processing unit is operable to perform a first function. Each of the plurality of functional logic blocks is operable to perform a respective function. The programmable logic is operable to route data to and from various ones of the plurality of functional logic blocks. The programmable logic is programmable to configure operation of two or more of the plurality of functional logic blocks and is also programmable to create data paths between two or of the plurality of functional logic blocks to configure the integrated circuit for one of the plurality of functions. The plurality of I/O pads is coupled to the main system processing unit and the plurality of functional logic blocks. The I/O pads are operable to transfer data signals between the integrated circuit and an external device. The programmable logic may perform a function different from each of the plurality of functional logic blocks. The system for programming the integrated circuit includes a computer system, the integrated circuit, and a cable for coupling the two.

摘要翻译： 一种集成电路，包括可以使用用于多个可能功能的多个可编程逻辑单元来扩展的主系统处理单元，以及用于对其进行编程的系统。 集成电路还包括多个功能逻辑块，多个输入/输出（I / O）焊盘和耦合到多个功能逻辑块中的每一个的可编程逻辑。 主系统处理单元可操作以执行第一功能。 多个功能逻辑块中的每一个可操作以执行相应的功能。 可编程逻辑可操作用于将数据路由到多个功能逻辑块中的各个功能逻辑块。 可编程逻辑可编程以配置多个功能逻辑块中的两个或更多个的操作，并且还可编程以在两个或多个功能逻辑块之间创建数据路径，以将集成电路配置为多个功能之一。 多个I / O焊盘耦合到主系统处理单元和多个功能逻辑块。 I / O焊盘可操作以在集成电路和外部设备之间传输数据信号。 可编程逻辑可以执行与多个功能逻辑块中的每一个功能不同的功能。 用于编程集成电路的系统包括计算机系统，集成电路和用于耦合两者的电缆。

公开(公告)号：US06341367B1

公开(公告)日：2002-01-22

申请号：US09624932

申请日：2000-07-25

申请人： Kevin A. Downing

发明人： Kevin A. Downing

IPC分类号： H03K17693

CPC分类号： G06F7/00 ,  G05B19/045 ,  G05B2219/23289

摘要： A state machine is disclosed that is capable of providing improved performance as realized in a hardware embodiment while providing the flexibility of a software implemented state machine. The state machine is first implemented in software, and then is realized in a hardware embodiment based upon the software implemented state machine. Flexibility is added to the hardware realized state machine by providing registers for the hardware embodiment so that the register corresponds to states of the software implementation. As a result, at least one aspect of the hardware realized state machine may be modified without requiring redesigning the configuration of the hardware embodiment. The performance of the state machine is improved by providing a separate state machine for receiving incoming data packets so that a main state machine is capable of operating without interruption by the incoming data packets and is capable of receiving the incoming data packets from the separate, incoming data packet receiving state machine only when the main state machine is ready to receive the incoming information. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 公开了一种状态机，其能够提供在硬件实施例中实现的改进的性能，同时提供软件实现的状态机的灵活性。 状态机首先以软件实现，然后在基于软件实现的状态机的硬件实施例中实现。 通过提供硬件实施例的寄存器将灵活性添加到硬件实现状态机，使得寄存器对应于软件实现的状态。 结果，可以修改硬件实现的状态机的至少一个方面，而不需要重新设计硬件实施例的配置。 通过提供用于接收输入数据分组的单独的状态机来改善状态机的性能，使得主状态机能够在输入数据分组不中断的情况下运行，并且能够从分离的输入接收输入数据分组 数据包接收状态机只有当主状态机准备好接收传入信息时。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他研究人员快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US06285237B1

公开(公告)日：2001-09-04

申请号：US09136592

申请日：1998-08-19

申请人： Joseph C. Sher

发明人： Joseph C. Sher

IPC分类号： H03K17693

CPC分类号： H03K19/1732 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An inventive integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

公开(公告)号：US06737890B2

公开(公告)日：2004-05-18

申请号：US10073363

申请日：2002-02-13

申请人： Toshikazu Hirai ,  Tetsuro Asano

发明人： Toshikazu Hirai ,  Tetsuro Asano

IPC分类号： H03K17693

CPC分类号： H01L27/0605 ,  H01L23/4824 ,  H01L2924/0002 ,  H03K17/693 ,  H03K2217/0036 ,  H01L2924/00

摘要： A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs.

摘要翻译： 开关电路器件具有第一FET和第二FET，并且具有单个控制端子。 该器件还具有连接到两个FET的漏极或源电极的公共输入端子，连接到相应FET的源极或漏极的第一输出端子和第二输出端子，偏置元件施加偏压 第一输出端子，将控制端子连接到第二FET的第一连接，将第二FET的栅极连接到地的第二连接，以及放置在两个FET之间的直流隔离元件。

公开(公告)号：US06646481B2

公开(公告)日：2003-11-11

申请号：US09972417

申请日：2001-10-04

申请人： Tim Blankenship ,  Stephen Bily

发明人： Tim Blankenship ,  Stephen Bily

IPC分类号： H03K17693

CPC分类号： H03F1/301 ,  G05F3/262 ,  G09G3/3685 ,  G09G2310/0291 ,  H03F3/04 ,  H03F3/345 ,  H03F3/45183 ,  H03F2200/78

摘要： Improved techniques for controlling current flow in an amplifier circuit provide steering of analog outputs of digital to analog converters and a full range of voltage output without necessitating a full range amplifier configuration and can be realized in a small space on an IC chip.

摘要翻译： 用于控制放大器电路中的电流的改进技术提供数字到模拟转换器的模拟输出的转向和全范围的电压输出，而不需要全范围的放大器配置，并且可以在IC芯片上的小空间中实现。

公开(公告)号：US06269469B1

公开(公告)日：2001-07-31

申请号：US09062418

申请日：1998-04-17

申请人： Ivan Pavisic ,  Ranko Scepanovic ,  Pedja Raspopovic

发明人： Ivan Pavisic ,  Ranko Scepanovic ,  Pedja Raspopovic

IPC分类号： H03K17693

CPC分类号： G06F17/5077

摘要： A method for implementing net routing for an integrated circuit design with parallel processors, said method comprising the steps of creating a character array, filling said character array with a first character, dividing a plurality of nets into groups, supplying a plurality of locks and assigning each said group its own individual lock, assigning for each net in said plurality of nets a position in the character array; and placing a second character in the position of a particular net in said character array when the net is operated on by a processor and replacing said second character with the first character after said operation is completed.

摘要翻译： 一种用于实现具有并行处理器的集成电路设计的网络路由的方法，所述方法包括以下步骤：创建字符阵列，用第一字符填充所述字符阵列，将多个网络划分成组，提供多个锁定和分配 每个所述组别自己的个人锁定，为所述多个网络中的每个网络分配字符阵列中的位置; 以及当所述网络由处理器操作并且在所述操作完成之后用所述第一字符替换所述第二字符时，将第二字符放置在所述字符阵列中的特定网络的位置。