公开(公告)号：US06707713B1

公开(公告)日：2004-03-16

申请号：US09516478

申请日：2000-03-01

申请人： Allan Parker ,  Joseph Skrovan ,  Brett Gerhardt

发明人： Allan Parker ,  Joseph Skrovan ,  Brett Gerhardt

IPC分类号： G11C1604

CPC分类号： G11C11/5642

摘要： A memory device having a plurality of multi-bit cells that are programmed with interlaced data provide superior read access time. The multi-bit cells are read by reading the first bit of each of the plurality of cells sequentially using a first reference voltage then reading the second bit of a first subset of the plurality of cells sequentially using a second reference voltage then reading the second bit of a second subset of the plurality of cells sequentially using a third reference voltage. The second reference voltage being higher and the third reference voltage being lower than the first reference voltage.

摘要翻译： 具有以隔行数据编程的多个多位单元的存储器件提供优异的读访问时间。 通过使用第一参考电压顺序读取多个单元中的每一个的第一位来读取多位单元，然后使用第二参考电压依次读取多个单元的第一子集的第二位，然后读取第二位 顺序地使用第三参考电压的多个单元的第二子集。 第二参考电压较高，第三参考电压低于第一参考电压。