公开(公告)号：US06707713B1

公开(公告)日：2004-03-16

申请号：US09516478

申请日：2000-03-01

申请人： Allan Parker ,  Joseph Skrovan ,  Brett Gerhardt

发明人： Allan Parker ,  Joseph Skrovan ,  Brett Gerhardt

IPC分类号： G11C1604

CPC分类号： G11C11/5642

摘要： A memory device having a plurality of multi-bit cells that are programmed with interlaced data provide superior read access time. The multi-bit cells are read by reading the first bit of each of the plurality of cells sequentially using a first reference voltage then reading the second bit of a first subset of the plurality of cells sequentially using a second reference voltage then reading the second bit of a second subset of the plurality of cells sequentially using a third reference voltage. The second reference voltage being higher and the third reference voltage being lower than the first reference voltage.

摘要翻译： 具有以隔行数据编程的多个多位单元的存储器件提供优异的读访问时间。 通过使用第一参考电压顺序读取多个单元中的每一个的第一位来读取多位单元，然后使用第二参考电压依次读取多个单元的第一子集的第二位，然后读取第二位 顺序地使用第三参考电压的多个单元的第二子集。 第二参考电压较高，第三参考电压低于第一参考电压。

公开(公告)号：US06400624B1

公开(公告)日：2002-06-04

申请号：US09794479

申请日：2001-02-26

申请人： Allan Parker ,  Joseph Skrovan

发明人： Allan Parker ,  Joseph Skrovan

IPC分类号： G11C2900

CPC分类号： G11C29/028 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/50 ,  G11C29/50004

摘要： A method for testing a multi-level memory includes storing multi-level data in a plurality of memory cells of the multi-level memory and reading from configure registers initial values of a plurality of performance variables. The performance variables set operating parameters of the multi-level memory. The method further includes during a first test phase operating the multi-level memory at the initial values of the plurality of performance variables and reading program values of the plurality of performance variables. During a second test phase, the multi-level memory is operated at the program values of the plurality of performance variables.

摘要翻译： 用于测试多级存储器的方法包括将多级数据存储在多级存储器的多个存储单元中，并从配置寄存器读取多个性能变量的初始值。 性能变量设置多级存储器的操作参数。 该方法还包括在第一测试阶段期间以多个性能变量的初始值操作多级存储器并读取多个性能变量的程序值。 在第二测试阶段期间，多级存储器以多个性能变量的程序值运行。

公开(公告)号：US06684353B1

公开(公告)日：2004-01-27

申请号：US09733252

申请日：2000-12-07

申请人： Allan Parker ,  Joseph Skrovan

发明人： Allan Parker ,  Joseph Skrovan

IPC分类号： G11C2900

CPC分类号： G11C29/44 ,  G11C2029/1208

摘要： An integrated reliability monitor that automatically tests a memory device until a threshold number of errors has been detected. The integrated reliability monitor eliminates the need for sophisticated external test equipment by automatically testing the memory cells in the memory array and providing the results. An optional programmable registers may store the error threshold value. The programmable registers may also store a time-out value or the reliability monitor may be externally interrupted.

摘要翻译： 一个集成的可靠性监视器，自动测试存储设备，直到检测到阈值数量的错误。 集成可靠性监视器通过自动测试存储器阵列中的存储单元并提供结果，无需复杂的外部测试设备。 可选的可编程寄存器可以存储错误阈值。 可编程寄存器也可以存储超时值，或者可以从外部中断可靠性监视器。

公开(公告)号：US06785856B1

公开(公告)日：2004-08-31

申请号：US09732616

申请日：2000-12-07

申请人： Allan Parker ,  Joseph Skrovan

发明人： Allan Parker ,  Joseph Skrovan

IPC分类号： G01R3128

CPC分类号： G11C29/12015 ,  G11C29/42 ,  G11C29/46 ,  G11C29/56012 ,  G11C2029/1208

摘要： An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store the results of the tests. The results may be transmitted from the memory device. The integrated memory self-tester may be initiated via a test signal, be self initiated periodically, or be initiated by other means.

摘要翻译： 测试整个存储器阵列的集成内存自检器件减少了对复杂的外部测试设备的需求，并缩短了测试的持续时间。 存储器阵列的读取测试可以检查存储单元。 可选的可编程寄存器可以存储测试结果。 结果可以从存储器件传输。 集成存储器自测试器可以经由测试信号启动，可以周期性自我启动，或者由其他方式启动。

公开(公告)号：US06424569B1

公开(公告)日：2002-07-23

申请号：US09513027

申请日：2000-02-25

申请人： Allan Parker ,  Joseph Skrovan

发明人： Allan Parker ,  Joseph Skrovan

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5641

摘要： A user selectable option to a memory cell, such as a multilevel NAND flash cell, that allows the user to select to optimize programming time or the data integrity. A programmable memory cell can have multiple programming modes. A mode selector can switch the programming of each cell or group of cells between the programming modes. A first programming mode can program the cell with a first programming voltage and maintaining at least a fifty percent of the maximum data margin. A second programming mode can program the cell with a second programming voltage and maintaining at least an eighty five percent of the maximum data margin. The first programming voltage can be greater than the second programming voltage.

摘要翻译： 存储器单元（诸如多级NAND闪存单元）的用户可选择选项，其允许用户选择优化编程时间或数据完整性。 可编程存储单元可以具有多种编程模式。 模式选择器可以在编程模式之间切换每个单元或单元组的编程。 第一编程模式可以用第一编程电压对单元进行编程并且保持至少百分之五十的最大数据容限。 第二编程模式可以用第二编程电压对单元进行编程，并且至少保持最大数据容限的百分之八十五。 第一编程电压可以大于第二编程电压。

公开(公告)号：US5960457A

公开(公告)日：1999-09-28

申请号：US846651

申请日：1997-05-01

申请人： Joseph Skrovan ,  Royce K. Presley ,  Hamilton B. Carter

发明人： Joseph Skrovan ,  Royce K. Presley ,  Hamilton B. Carter

IPC分类号： G06F12/08 ,  G11C29/02 ,  G11C29/10 ,  G11C29/50 ,  G06F12/00

CPC分类号： G11C29/50012 ,  G06F12/0831 ,  G11C29/02 ,  G11C29/50 ,  G06F2212/1032 ,  G11C15/00 ,  G11C29/10

摘要： A test methodology for a cache memory subsystem includes setting a test unit to initiate a snoop cycle on a local bus upon lapse of a predetermined delay. The predetermined delay is initially set to a very short delay or a zero delay. The snoop cycle to be executed may take the form of an inquire cycle to a predetermined memory address. The test unit is further set or programmed to begin monitoring the local bus for certain activity including activity which is indicative of whether the snoop cycle occurred. After programming the test unit, the processor core executes a memory operation associated with the address of the snoop cycle. This memory operation causes a cache line transition. At some point, either before, during or after effectuation of the memory operation, the snoop cycle is executed by the test unit in accordance with the predetermined delay. Upon completing the memory operation, a status register is read from the test unit to determine whether the snoop cycle has yet occurred. If the snoop cycle occurred prior to completing the memory operation, the predetermined delay is increased and the test is repeated for the increased delay. Prior to repeating the test, the cache line's coherency with external memory is checked for conformance with the cache protocol. Additionally, the test unit may further be programmed to detect an occurrence of certain external local bus signals generated by the cache memory subsystem, such as a signal indicating a hit to a cache line occurred, and a signal indicating that a hit to a modified line in the cache occurred. The test is repeated until it is determined that the snoop cycle has not occurred upon completion of the line fill instruction.

摘要翻译： 高速缓存存储器子系统的测试方法包括设置测试单元以在经过预定延迟时在局部总线上发起窥探周期。 预定的延迟最初被设置为非常短的延迟或零延迟。 要执行的侦听周期可以以查询周期的形式到预定的存储器地址。 测试单元进一步设置或编程为开始监视局部总线的某些活动，包括指示是否发生窥探周期的活动。 在对测试单元进行编程之后，处理器核心执行与窥探周期的地址相关联的存储器操作。 该存储器操作导致高速缓存行转换。 在某一时刻，在存储器操作之前，期间或之后，通过测试单元根据预定的延迟执行窥探周期。 在完成存储器操作时，从测试单元读取状态寄存器以确定窥探周期是否仍然发生。 如果在完成存储器操作之前发生探听周期，则增加预定延迟并且为了延长延迟重复测试。 在重复测试之前，检查缓存行与外部存储器的一致性是否符合缓存协议。 此外，测试单元还可以被编程为检测由高速缓存存储器子系统产生的某些外部局部总线信号的发生，例如指示发生高速缓存线的命中的信号，以及指示对修改的线的命中的信号 在缓存中发生。 重复该测试，直到确定在行填充指令完成后探测周期未发生。

公开(公告)号：US6091631A

公开(公告)日：2000-07-18

申请号：US108529

申请日：1998-07-01

申请人： Joe Kucera ,  Joseph Skrovan

发明人： Joe Kucera ,  Joseph Skrovan

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C16/3454

摘要： A program/verify method for a multi-level flash memory array, wherein threshold values to be programmed into each flash memory cell are represented using binary bits. In the program/verify method for each cell, the most significant bit representing the threshold level to be programmed into a cell is read first and the cell is programmed to the minimum threshold level represented by the most significant bit. The next most significant bit is then read and if necessary further programming pulses are applied to complete programming. By programming to the level of the most significant bit first rather than programming to each possible threshold separately as determined by all bits read together, less time is required for programming an array.

摘要翻译： 一种用于多级闪存阵列的程序/验证方法，其中使用二进制位来表示要编程到每个闪存单元中的阈值。 在每个单元的编程/验证方法中，首先读取表示要编程到单元中的阈值电平的最高有效位，并将单元编程为由最高有效位表示的最小阈值电平。 然后读取下一个最高有效位，并且如果需要，则应用另外的编程脉冲来完成编程。 通过编程到最高有效位的电平而不是编程到每个可能的阈值，单独地由所有位读取确定，所以编程阵列需要更少的时间。