Nonplanar device with stress incorporation layer and method of fabrication
    1.
    发明申请
    Nonplanar device with stress incorporation layer and method of fabrication 有权
    具有应力结合层的非平面器件及其制造方法

    公开(公告)号:US20060261411A1

    公开(公告)日:2006-11-23

    申请号:US11493789

    申请日:2006-07-25

    IPC分类号: H01L27/12

    摘要: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

    摘要翻译: 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极,并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜,其中薄膜在半导体本体中产生应力。