公开(公告)号：US12113131B2

公开(公告)日：2024-10-08

申请号：US17633804

申请日：2020-08-07

申请人： Hitachi Energy Ltd

发明人： Stephan Wirths ,  Lars Knoll

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/51 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/7843 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66333 ,  H01L29/66666 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7847 ,  H01L29/7849

摘要： A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

公开(公告)号：US12002876B2

公开(公告)日：2024-06-04

申请号：US18084912

申请日：2022-12-20

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Kenichi Okazaki ,  Junichi Koezuka ,  Tomonori Nakayama ,  Motoki Nakashima

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L29/66969 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/7849 ,  H01L29/786

摘要： In a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The transistor includes an oxide semiconductor film over a first insulating film; a second insulating film over the oxide semiconductor film; a metal oxide film over the second insulating film; a gate electrode over the metal oxide film; and a third insulating film over the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The source region and the drain region contain one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas.

公开(公告)号：US11978771B2

公开(公告)日：2024-05-07

申请号：US18069278

申请日：2022-12-21

申请人： Atomera Incorporated

发明人： Keith Doran Weeks ,  Nyles Wynn Cody ,  Marek Hytha ,  Robert J. Mears ,  Robert John Stephenson ,  Hideki Takeuchi

IPC分类号： H01L29/15 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/152 ,  H01L29/66477 ,  H01L29/7849

摘要： A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：US20240145480A1

公开(公告)日：2024-05-02

申请号：US18326841

申请日：2023-05-31

申请人： STMICROELECTRONICS, INC.

发明人： John H. ZHANG

IPC分类号： H01L27/12 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B20/00

CPC分类号： H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H10B10/12 ,  H10B10/125 ,  H10B20/27 ,  H01L2924/0002

摘要： Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US20240006532A1

公开(公告)日：2024-01-04

申请号：US18465050

申请日：2023-09-11

申请人： Acorn Semi, LLC

发明人： Paul A. Clifton ,  Andreas Goebel

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/7849 ,  H01L29/0649 ,  H01L27/1203 ,  H01L21/76283 ,  H01L21/02381 ,  H01L21/76254 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7846 ,  H01L29/105

摘要： A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

公开(公告)号：US11791411B2

公开(公告)日：2023-10-17

申请号：US17657854

申请日：2022-04-04

申请人： Acorn Semi, LLC

发明人： Paul A. Clifton ,  Andreas Goebel

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76254 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848

摘要： A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

公开(公告)号：US20230260971A1

公开(公告)日：2023-08-17

申请号：US17669788

申请日：2022-02-11

申请人： International Business Machines Corporation

发明人： Shogo Mochizuki ,  Kangguo Cheng ,  Juntao Li

IPC分类号： H01L25/07 ,  H01L29/78 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/074 ,  H01L29/7849 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/13091

摘要： A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.

公开(公告)号：US11705458B2

公开(公告)日：2023-07-18

申请号：US17159013

申请日：2021-01-26

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L27/12 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78 ,  H10B10/00 ,  H10B20/00

CPC分类号： H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H10B10/12 ,  H10B10/125 ,  H10B20/27 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US20190123049A1

公开(公告)日：2019-04-25

申请号：US16222081

申请日：2018-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yong-Yan Lu ,  Chia-Wei Soong ,  Hou-Yu Chen

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/0921 ,  H01L21/2255 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7849 ,  H01L29/785

摘要： A semiconductor device includes a substrate, an isolation structure over the substrate, and a first semiconductor layer over the substrate. At least a portion of the first semiconductor layer is surrounded by the isolation structure. The semiconductor device further includes a doped material layer between the isolation structure and the first semiconductor layer.

公开(公告)号：US20190006241A1

公开(公告)日：2019-01-03

申请号：US15725174

申请日：2017-10-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Che-Wei YANG ,  Hao-Hsiung LIN ,  Samuel C. PAN

IPC分类号： H01L21/8234 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.