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公开(公告)号:US20050093577A1
公开(公告)日:2005-05-05
申请号:US10701667
申请日:2003-11-04
申请人: Liem Nguyen , Xiaojie He , Brian Gaide , Kerry Ilgenstein , Sajitha Wijesuriya , Claudia Stanley , Aaron Rogers , Zheng Chen
发明人: Liem Nguyen , Xiaojie He , Brian Gaide , Kerry Ilgenstein , Sajitha Wijesuriya , Claudia Stanley , Aaron Rogers , Zheng Chen
IPC分类号: H03K3/356 , H03K17/693 , H03K19/094
CPC分类号: H03K3/356008 , H03K17/693
摘要: Multiplexer circuits are disclosed, such as for example for programmable logic devices. As an example of one embodiment, a multiplexer circuit is disclosed having a default state and a state-locking latch.
摘要翻译: 公开了多路复用器电路,例如用于可编程逻辑器件。 作为一个实施例的示例,公开了具有默认状态和状态锁定锁存器的多路复用器电路。
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公开(公告)号:US07685215B1
公开(公告)日:2010-03-23
申请号:US11257137
申请日:2005-10-24
申请人: Brian Gaide , Xiaojie He
发明人: Brian Gaide , Xiaojie He
CPC分类号: G06F7/508
摘要: In one embodiment of the invention, programmable circuits, such as FPGAs, may be used to implement different types of functions, such as a multi-bit adder, using look-up table (LUT) circuits as their building blocks. Efficient generation of carry-out signals and fast-carry generation signals using available SRAM cells in the various embodiments of the LUT circuit can reduce and/or eliminate area-inefficient look-ahead carry logic without a significant delay in signal generation.
摘要翻译: 在本发明的一个实施例中,诸如FPGA之类的可编程电路可以用于实现不同类型的功能,例如使用查找表(LUT)电路作为其构建块的多位加法器。 在LUT电路的各种实施例中,利用可用的SRAM单元有效地产生进位信号和快速携带产生信号可以减少和/或消除无效率的先行进位逻辑,而不会产生显着的信号延迟。
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