High contrast alignment marker for integrated circuit fabrication
    1.
    发明授权
    High contrast alignment marker for integrated circuit fabrication 失效
    用于集成电路制造的高对比度对准标记

    公开(公告)号:US4374915A

    公开(公告)日:1983-02-22

    申请号:US288519

    申请日:1981-07-30

    IPC分类号: G03F9/00 G03C11/00

    CPC分类号: G03F9/7076 G03F9/00

    摘要: A wafer marker is described for aligning masks with the wafer. The marker comprises a depression in the wafer which is defined by sloped sides and a pitted bottom. The sloped sides and pitted bottom do not directly reflect light as does the surface of the surrounding silicon and thus the marker appears as a darker region. The bottom of the depression is pitted by exposing the anode during a silicon plasma etching step.

    摘要翻译: 描述了用于将掩模与晶片对准的晶片标记。 标记包括由倾斜侧面和凹陷底部限定的晶片中的凹陷。 倾斜的侧面和凹陷的底部不像周围的硅的表面那样直接反射光,因此标记显示为较暗的区域。 通过在硅等离子体蚀刻步骤期间暴露阳极来凹陷凹陷的底部。

    Variable thickness self-aligned photoresist process
    2.
    发明授权
    Variable thickness self-aligned photoresist process 失效
    可变厚度自对准光刻胶工艺

    公开(公告)号:US4231811A

    公开(公告)日:1980-11-04

    申请号:US75095

    申请日:1979-09-13

    摘要: A process for forming with a single masking step regions of different thicknesses in a photo-sensitive layer is disclosed. A masking member or reticle includes opaque and transparent areas and areas with a grating. The pitch of the periodic grating is of a lesser dimension than can be resolved by the masking projection apparatus. The photo-sensitive region illuminated by the grating receives uniform illumination at an intermediate intensity, thereby providing, after developing, a layer with regions of intermediate thickness.

    摘要翻译: 公开了一种在光敏层中用不同厚度的单个掩模步骤形成区域的方法。 掩模构件或掩模版包括不透明区域和具有光栅的区域。 周期光栅的间距比由掩模投影装置可以解析的尺寸小。 由光栅照射的光敏区域以中等强度接收均匀的照明,从而在显影之后提供具有中等厚度的区域的层。