公开(公告)号：US11769662B2

公开(公告)日：2023-09-26

申请号：US17206908

申请日：2021-03-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Lin Chang ,  Chih-Chien Wang ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Chien-Hung Lin ,  Chun-Chang Chen ,  Ching-Sen Kuo ,  Feng-Jia Shiu

IPC分类号： H01L21/02 ,  H01L21/027

CPC分类号： H01L21/0206 ,  H01L21/0277

摘要： Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

公开(公告)号：US10018920B2

公开(公告)日：2018-07-10

申请号：US15061860

申请日：2016-03-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Hao Chang ,  Kuo-Chang Kau ,  Kevin Huang ,  Jeng-Horng Chen

IPC分类号： G03F7/004 ,  G03F7/11 ,  G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  G03F7/40 ,  B05D1/00 ,  B05D3/06 ,  H01L21/027 ,  H01L21/311 ,  H01L21/687 ,  H01L21/02

CPC分类号： G03F7/70341 ,  B05D1/60 ,  B05D3/06 ,  B05D3/061 ,  B05D3/068 ,  G03F7/0042 ,  G03F7/038 ,  G03F7/11 ,  G03F7/167 ,  G03F7/2004 ,  G03F7/201 ,  G03F7/2037 ,  G03F7/2039 ,  G03F7/38 ,  G03F7/40 ,  G03F7/70325 ,  H01L21/02118 ,  H01L21/02277 ,  H01L21/0271 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/687 ,  H01L21/68764

摘要： Disclosed is a method for lithography patterning. The method includes providing a substrate, forming a deposition enhancement layer (DEL) over the substrate, and flowing an organic gas near a surface of the DEL. During the flowing of the organic gas, the method further includes irradiating the DEL and the organic gas with a patterned radiation. Elements of the organic gas polymerize upon the patterned radiation, thereby forming a resist pattern over the DEL. The method further includes etching the DEL with the resist pattern as an etch mask, thereby forming a patterned DEL.

公开(公告)号：US10014184B2

公开(公告)日：2018-07-03

申请号：US14916557

申请日：2014-09-04

申请人： Applied Materials, Inc.

发明人： Christopher D. Bencher

IPC分类号： H01L21/302 ,  H01L21/3105 ,  H01L21/027 ,  B24B37/015 ,  B24B37/04 ,  G03F7/00 ,  G03F7/09 ,  B24B37/20 ,  H01L23/528

CPC分类号： H01L21/31058 ,  B24B37/015 ,  B24B37/04 ,  B24B37/20 ,  G03F7/0035 ,  G03F7/094 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/31056 ,  H01L23/528

摘要： Methods, apparatus, and systems are provided for forming a resist array on a material to be patterned using chemical-mechanical planarization. The resist array may include an arrangement of two different materials that are adapted to react to activation energy differently relative to each other to enable selective removal of only one of the materials (e.g., one is reactive and the other is not reactive; one is slightly reactive and the other is very reactive; one is reactive in one domain and the other in an opposite domain). The first material may be disposed as isolated nodes between the second material. A subset of nodes may be selected from among the nodes in the array and the selected nodes may be exposed to activation energy to activate the nodes and create a mask from the resist array. Numerous additional aspects are disclosed.

公开(公告)号：US09952511B2

公开(公告)日：2018-04-24

申请号：US15122403

申请日：2014-12-19

申请人： Intel Corporation

发明人： Yan A. Borodovsky ,  Donald W. Nelson ,  Mark C. Phillips

IPC分类号： G03F7/20 ,  H01J37/30 ,  H01J37/06 ,  H01J37/147 ,  H01L21/027 ,  H01J37/317 ,  H01L21/311

CPC分类号： G03F7/2037 ,  H01J37/045 ,  H01J37/06 ,  H01J37/1474 ,  H01J37/3007 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01J2237/31776 ,  H01J2237/31796 ,  H01L21/0277 ,  H01L21/31144

摘要： Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA is a non-universal cutter.

公开(公告)号：US20180090577A1

公开(公告)日：2018-03-29

申请号：US15685063

申请日：2017-08-24

申请人： FUJITSU LIMITED

发明人： Kozo Makiyama

IPC分类号： H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H03F3/193

CPC分类号： H01L29/408 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02241 ,  H01L21/02274 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/0277 ,  H01L21/30621 ,  H01L21/31116 ,  H01L21/31144 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H02M1/4208 ,  H02M5/4585 ,  H03F1/3205 ,  H03F1/3241 ,  H03F1/3247 ,  H03F3/1935 ,  H03F3/195 ,  H03F3/21 ,  H03F3/245 ,  H03F2200/451

摘要： A compound semiconductor device disclosed herein includes a substrate, an electron transit layer formed on the substrate, a compound semiconductor layer containing gallium and formed on the electron transit layer, a diffusion preventing layer containing gallium oxide and formed on the compound semiconductor layer, an insulation layer formed on the diffusion preventing layer, and a source electrode, a drain electrode, and a gate electrode formed over the electron transit layer at a distance from one another.

公开(公告)号：US09685367B2

公开(公告)日：2017-06-20

申请号：US15394466

申请日：2016-12-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Cheng Lu ,  Chih-Tsung Shih ,  Shinn-Sheng Yu ,  Jeng-Horng Chen ,  Anthony Yen

IPC分类号： H01L21/033 ,  H01L21/768 ,  G03F7/095 ,  G03F7/039 ,  H01L21/311 ,  G03F7/20 ,  G03F1/22

CPC分类号： H01L21/76817 ,  G03F1/20 ,  G03F1/22 ,  G03F1/50 ,  G03F1/58 ,  G03F7/039 ,  G03F7/095 ,  G03F7/20 ,  G03F7/2004 ,  H01L21/0277 ,  H01L21/0332 ,  H01L21/3083 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76877

摘要： The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern.

公开(公告)号：US20170110366A1

公开(公告)日：2017-04-20

申请号：US15394466

申请日：2016-12-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Cheng LU ,  Chih-Tsung SHIH ,  Shinn-Sheng YU ,  Jeng-Horng CHEN ,  Anthony YEN

IPC分类号： H01L21/768 ,  G03F1/22 ,  H01L21/311 ,  G03F7/20 ,  G03F7/095 ,  G03F7/039

CPC分类号： H01L21/76817 ,  G03F1/20 ,  G03F1/22 ,  G03F1/50 ,  G03F1/58 ,  G03F7/039 ,  G03F7/095 ,  G03F7/20 ,  G03F7/2004 ,  H01L21/0277 ,  H01L21/0332 ,  H01L21/3083 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76877

摘要： The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern.

公开(公告)号：US20170077029A1

公开(公告)日：2017-03-16

申请号：US15122396

申请日：2014-12-19

申请人： Intel Corporation

发明人： Donald W. NELSON ,  Yan A. BORODOVSKY ,  Mark C. PHILLIPS

IPC分类号： H01L23/528 ,  H01L27/11 ,  H01L21/768 ,  H01L27/02

CPC分类号： H01L23/5283 ,  H01J37/045 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76886 ,  H01L27/0207 ,  H01L27/11

摘要： Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction. The layout also includes a second region having a plurality of unidirectional lines of a second width and a second pitch and parallel with the first direction, the second width and the second pitch different than the first width and the first pitch, respectively. The layout also includes a third region having a plurality of unidirectional lines of a third width and a third pitch and parallel with the first direction, the third width and the third pitch different than the first and second widths and different than the first and second pitches.

摘要翻译： 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，集成电路的金属化层的布局包括具有第一宽度和第一间距的多个单向线并与第一方向平行的第一区域。 布局还包括具有第二宽度和第二间距的多个单向线并且与第一方向平行的第二区域，第二宽度和第二间距分别与第一宽度和第一间距不同的第二区域。 布局还包括具有第三宽度和第三间距的多个单向线并且与第一方向平行的第三区域，第三宽度和第三间距不同于第一和第二宽度并且不同于第一和第二间距 。

公开(公告)号：US20170076967A1

公开(公告)日：2017-03-16

申请号：US15122792

申请日：2014-12-22

申请人： Intel Corporation

发明人： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC分类号： H01L21/68

CPC分类号： H01L21/682 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/24578 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

摘要： Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of real-time alignment of a wafer situated on a stage of an e-beam tool involves collecting backscattered electrons from an underlying patterned feature of the wafer while an e-beam column of the e-beam tool writes during scanning of the stage. The collecting is performed by an electron detector placed at the e-beam column bottom. The method also involves performing linear corrections of an alignment of the stage relative to the e-beam column based on the collecting.

摘要翻译： 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，位于电子束工具的台上的晶片的实时对准的方法涉及从电子束工具的电子束列的电子束列中收集来自晶片的底层图案化特征的反向散射电子， 扫描舞台。 收集由放置在电子束柱底部的电子检测器进行。 该方法还涉及基于收集来执行阶段相对于电子束列的对准的线性校正。

公开(公告)号：US09594018B2

公开(公告)日：2017-03-14

申请号：US15225286

申请日：2016-08-01

申请人： International Business Machines Corporation

发明人： Phaedon Avouris ,  Damon B. Farmer ,  Yilei Li ,  Hugen Yan

IPC分类号： G01N21/75 ,  G01N21/552 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/04

CPC分类号： G01N21/554 ,  H01L21/02422 ,  H01L21/02527 ,  H01L21/0277 ,  H01L21/041 ,  H01L21/042 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/56 ,  H01L29/1606

摘要： Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

摘要翻译： 提供了形成纳米薄片或体积石墨烯的SPR传感器的技术。 一方面，提供一种形成基于石墨烯的SPR传感器的方法，其包括以下步骤：将石墨烯沉积到衬底上，其中所述衬底包括导电层上的电介质层，并且其中所述石墨烯沉积在所述介电层上 ; 以及将所述石墨烯图案化成多个均匀间隔的石墨烯条，其中每个所述石墨烯条的宽度为约50纳米至约5微米，并且在其间的范围，并且其中所述石墨烯条彼此间隔开距离 约5纳米至约50微米，并且其间的范围。 或者，可以使用块状石墨烯，并且使用电介质层形成具有不同介电常数的周期性区域。 还提供了使用本SPR传感器分析样品的测试装置和方法。