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公开(公告)号：US20080055126A1
公开(公告)日：2008-03-06
申请号：US11851129
申请日：2007-09-06
申请人： Chaitanya Dudha , Tim Schoenauer , Paul Wallner
发明人： Chaitanya Dudha , Tim Schoenauer , Paul Wallner
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A device configured to parallelize N serial digital input signals includes at least M bit storage devices configured to each respectively store one bit of the N serial digital input signals and provide the one stored bit as a bit of a parallel digital output signal with a bit width M. M is greater than N and N is greater than 1. Symbols with a bit width M are transmitted via the N serial digital input signals such that each of the N serial digital input signals transmits a fraction of the respective symbol. A control device is configured to drive the plurality of bit storage devices cyclically such that at least M bits of the serial digital input signals, which belong to one symbol, are stored in the bit storage devices within a cycle.
摘要翻译： 被配置为并行N个串行数字输入信号的设备包括至少M位存储设备，其被配置为分别存储N个串行数字输入信号的一位，并将一个存储的位作为并行数字输出信号的比特宽度 M.M大于N且N大于1.具有位宽M的符号通过N个串行数字输入信号传输，使得N个串行数字输入信号中的每一个发送相应符号的一部分。 控制装置被配置为循环地驱动多个位存储装置，使得属于一个符号的串行数字输入信号的至少M位在一个周期内存储在位存储装置中。
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公开(公告)号：US20070204116A1
公开(公告)日：2007-08-30
申请号：US11679609
申请日：2007-02-27
申请人： Paul Wallner , Chaitanya Dudha
发明人： Paul Wallner , Chaitanya Dudha
CPC分类号： G06F12/0607
摘要： A memory arrangement includes an interface configured to transmit coding and/or decoding data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing, the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
摘要翻译： 存储器装置包括被配置为根据预定义的协议以数据分组的形式传输数据的编码和/或解码的接口。 存储器装置包括至少两个存储体，每个存储体包括至少一个存储单元。 存储器装置包括被配置为便于访问至少两个存储体中的每一个的至少一个存储单元的数据的至少两个存储体存取器存取器件。 存储器装置包括至少两个临时存储装置，其被配置为临时存储在接口和至少两个存储体存取装置之间传输的数据。 所述至少两个临时存储设备中的每一个连接到所述接口和所述至少两个存储体存取设备中的一个。
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公开(公告)号：US07536528B2
公开(公告)日：2009-05-19
申请号：US11679609
申请日：2007-02-27
申请人： Paul Wallner , Chaitanya Dudha
发明人： Paul Wallner , Chaitanya Dudha
IPC分类号： G06F13/00
CPC分类号： G06F12/0607
摘要： A memory arrangement includes an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
摘要翻译： 存储器布置包括被配置为按照预定义的协议以数据分组的形式传输，编码和/或解码数据的接口。 存储器装置包括至少两个存储体，每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其被配置为便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 存储器装置包括至少两个临时存储装置，其被配置为临时存储在接口和至少两个存储体存取装置之间传输的数据。 所述至少两个临时存储设备中的每一个连接到所述接口和所述至少两个存储体存取设备中的一个。
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公开(公告)号：US20080028148A1
公开(公告)日：2008-01-31
申请号：US11496261
申请日：2006-07-31
申请人： Paul Wallner , Chaitanya Dudha
发明人： Paul Wallner , Chaitanya Dudha
IPC分类号： G06F12/00
CPC分类号： G06F12/023
摘要： An integrated memory device includes a memory core having a plurality of memory cells and a group of terminals for communication between the memory device and an external electronic device. A data buffer temporarily stores data. The data buffer is coupled to the group of terminals and to the memory core. The data buffer includes a plurality of data buffer sections. Each data buffer section is capable of temporarily storing at least one data frame and being accessible by a respective data buffer address. A data buffer control unit is also provided.
摘要翻译： 集成存储器件包括具有多个存储器单元的存储器芯和用于存储器件和外部电子器件之间的通信的一组端子。 数据缓冲器临时存储数据。 数据缓冲器耦合到终端组和存储器核心。 数据缓冲器包括多个数据缓冲器部分。 每个数据缓冲器部分能够临时存储至少一个数据帧并且可由相应的数据缓冲器地址访问。 还提供了数据缓冲器控制单元。
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公开(公告)号：US07515075B1
公开(公告)日：2009-04-07
申请号：US11856353
申请日：2007-09-17
IPC分类号： H03M9/00
摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.
摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。
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公开(公告)号：US20090073010A1
公开(公告)日：2009-03-19
申请号：US11856353
申请日：2007-09-17
IPC分类号： H03M9/00
摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.
摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。
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