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公开(公告)号：US07515075B1
公开(公告)日：2009-04-07
申请号：US11856353
申请日：2007-09-17
IPC分类号： H03M9/00
摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.
摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。
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公开(公告)号：US20090073010A1
公开(公告)日：2009-03-19
申请号：US11856353
申请日：2007-09-17
IPC分类号： H03M9/00
摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.
摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。
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公开(公告)号：US20070204116A1
公开(公告)日：2007-08-30
申请号：US11679609
申请日：2007-02-27
申请人： Paul Wallner , Chaitanya Dudha
发明人： Paul Wallner , Chaitanya Dudha
CPC分类号： G06F12/0607
摘要： A memory arrangement includes an interface configured to transmit coding and/or decoding data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing, the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
摘要翻译： 存储器装置包括被配置为根据预定义的协议以数据分组的形式传输数据的编码和/或解码的接口。 存储器装置包括至少两个存储体，每个存储体包括至少一个存储单元。 存储器装置包括被配置为便于访问至少两个存储体中的每一个的至少一个存储单元的数据的至少两个存储体存取器存取器件。 存储器装置包括至少两个临时存储装置，其被配置为临时存储在接口和至少两个存储体存取装置之间传输的数据。 所述至少两个临时存储设备中的每一个连接到所述接口和所述至少两个存储体存取设备中的一个。
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公开(公告)号：US07536528B2
公开(公告)日：2009-05-19
申请号：US11679609
申请日：2007-02-27
申请人： Paul Wallner , Chaitanya Dudha
发明人： Paul Wallner , Chaitanya Dudha
IPC分类号： G06F13/00
CPC分类号： G06F12/0607
摘要： A memory arrangement includes an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
摘要翻译： 存储器布置包括被配置为按照预定义的协议以数据分组的形式传输，编码和/或解码数据的接口。 存储器装置包括至少两个存储体，每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其被配置为便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 存储器装置包括至少两个临时存储装置，其被配置为临时存储在接口和至少两个存储体存取装置之间传输的数据。 所述至少两个临时存储设备中的每一个连接到所述接口和所述至少两个存储体存取设备中的一个。
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公开(公告)号：US20080028148A1
公开(公告)日：2008-01-31
申请号：US11496261
申请日：2006-07-31
申请人： Paul Wallner , Chaitanya Dudha
发明人： Paul Wallner , Chaitanya Dudha
IPC分类号： G06F12/00
CPC分类号： G06F12/023
摘要： An integrated memory device includes a memory core having a plurality of memory cells and a group of terminals for communication between the memory device and an external electronic device. A data buffer temporarily stores data. The data buffer is coupled to the group of terminals and to the memory core. The data buffer includes a plurality of data buffer sections. Each data buffer section is capable of temporarily storing at least one data frame and being accessible by a respective data buffer address. A data buffer control unit is also provided.
摘要翻译： 集成存储器件包括具有多个存储器单元的存储器芯和用于存储器件和外部电子器件之间的通信的一组端子。 数据缓冲器临时存储数据。 数据缓冲器耦合到终端组和存储器核心。 数据缓冲器包括多个数据缓冲器部分。 每个数据缓冲器部分能够临时存储至少一个数据帧并且可由相应的数据缓冲器地址访问。 还提供了数据缓冲器控制单元。
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公开(公告)号：US20080055126A1
公开(公告)日：2008-03-06
申请号：US11851129
申请日：2007-09-06
申请人： Chaitanya Dudha , Tim Schoenauer , Paul Wallner
发明人： Chaitanya Dudha , Tim Schoenauer , Paul Wallner
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A device configured to parallelize N serial digital input signals includes at least M bit storage devices configured to each respectively store one bit of the N serial digital input signals and provide the one stored bit as a bit of a parallel digital output signal with a bit width M. M is greater than N and N is greater than 1. Symbols with a bit width M are transmitted via the N serial digital input signals such that each of the N serial digital input signals transmits a fraction of the respective symbol. A control device is configured to drive the plurality of bit storage devices cyclically such that at least M bits of the serial digital input signals, which belong to one symbol, are stored in the bit storage devices within a cycle.
摘要翻译： 被配置为并行N个串行数字输入信号的设备包括至少M位存储设备，其被配置为分别存储N个串行数字输入信号的一位，并将一个存储的位作为并行数字输出信号的比特宽度 M.M大于N且N大于1.具有位宽M的符号通过N个串行数字输入信号传输，使得N个串行数字输入信号中的每一个发送相应符号的一部分。 控制装置被配置为循环地驱动多个位存储装置，使得属于一个符号的串行数字输入信号的至少M位在一个周期内存储在位存储装置中。
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7.发明授权Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals 有权具有时钟信号再生电路的存储器模块和用于临时存储输入命令和地址信号的寄存器电路公开(公告)号：US07334150B2
公开(公告)日：2008-02-19
申请号：US11002148
申请日：2004-12-03
申请人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F1/04
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。
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公开(公告)号：US20070047372A1
公开(公告)日：2007-03-01
申请号：US11509092
申请日：2006-08-24
申请人： Paul Wallner , Andre Schafer , Peter Gregorius
发明人： Paul Wallner , Andre Schafer , Peter Gregorius
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1051 , G11C2207/107
摘要： A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.
摘要翻译： 半导体存储器系统包括半导体存储器芯片，其中数据，命令和地址信号在与预定协议相对应的信号帧中的存储器控制器和半导体存储器芯片之间串行发送。 在半导体存储器芯片内的接收信号路径中，用于对信号帧进行解码的帧解码器被布置在接收接口设备之后，并且在帧解码器和存储器核心之间，布置中间存储设备，其具有包括单元阵列 多个存储器单元，以及寻址和选择器电路，由帧解码器从由存储器控制器提供的命令和/或写入信号帧解码的地址信号被应用于寻址单元阵列并用于选择要写入的写入数据 进入单元阵列并从单元阵列中读出。
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9.发明申请公开(公告)号：US20060291263A1
公开(公告)日：2006-12-28
申请号：US11128789
申请日：2005-05-13
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译： 公开了一种存储器系统和方法。 在一个实施例中，存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线被布置在分别指定的拓扑中。 连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。 将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。
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公开(公告)号：US20060193414A1
公开(公告)日：2006-08-31
申请号：US11345668
申请日：2006-02-02
申请人： Peter Gregorius , Paul Wallner
发明人： Peter Gregorius , Paul Wallner
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , G11C7/22 , G11C7/222 , G11C11/4076 , H03L7/0814 , H04L7/0337
摘要： A synchronization and data recovery device (SuD) for clock-synchronized recovery of data bits in a data stream is provided, which is particularly suitable for improved backward identification of data in serial receiver interfaces of high-speed semiconductor memory modules and/or memory controller modules with a low data density. The SuD includes a sampling unit, a data adjustment unit, a digital monitoring unit, a phase lock detector unit, a phase generator, an FIR low-pass filter and a data recovery decision unit. After synchronization of the values that have been sampled by the sampling unit in the data adjustment unit, these values are filtered in the FIR low-pass filter unit, which indicates a greater tolerance with respect to fluctuations in the ideal sampling time, in that it uses sample values of the previous symbol and of the subsequent symbol in addition to the sample values of the symbol to be identified.
摘要翻译： 提供了用于数据流中数据位的时钟同步恢复的同步和数据恢复设备（SuD），其特别适用于改进高速半导体存储器模块和/或存储器控制器的串行接收器接口中数据的向后标识 具有低数据密度的模块。 SuD包括采样单元，数据调整单元，数字监视单元，锁相检测器单元，相位发生器，FIR低通滤波器和数据恢复判定单元。 在由数据调整单元中的采样单元采样的值同步之后，这些值在FIR低通滤波器单元中被滤波，这表示相对于理想采样时间的波动具有更大的公差，因为它 除了要识别的符号的样本值之外，还使用先前符号和后续符号的采样值。
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