公开(公告)号：US5830772A

公开(公告)日：1998-11-03

申请号：US526073

申请日：1995-09-08

Applicant: Che-Pin Tseng ,  Nai-Jen Yeh ,  Yu-Chih Chuang ,  Cheng-Chih Kung

Inventor： Che-Pin Tseng ,  Nai-Jen Yeh ,  Yu-Chih Chuang ,  Cheng-Chih Kung

IPC: H01L21/761 ,  H01L21/8246 ,  H01L21/44 ,  H01L21/76

CPC classification number: H01L27/11293 ,  H01L21/761

Abstract: Although the spacers are formed on the sidewalls of gate electrode and words lines via the same steps of deposition and etch-back processes, only the spacers disposed at the sidewalls of the gate electrode are practical for fabricating peripheral devices with LDD structure, and such fabrication is impractical in the memory cell region. On the contrary, the region beneath the spacers disposed at the sidewalls of word lines will become the path through which leakage current flows. The present invention makes use a shielding layer to cover the second active region as a masking, and then removes the spacers disposed at the sidewalls of word lines. Afterwards, isolating regions are formed through one implantation procedure to thereby decrease leakage current and simplify the process flow.

Abstract translation: 虽然通过沉积和回蚀工艺的相同步骤在栅极和字线的侧壁上形成间隔物，但是仅设置在栅电极的侧壁处的间隔物实际上用于制造具有LDD结构的外围器件，并且这种制造 在记忆细胞区域是不切实际的。 相反，位于字线侧壁的间隔物下方的区域将成为漏电流流过的路径。 本发明利用屏蔽层覆盖作为掩蔽的第二有源区，然后去除设置在字线侧壁的间隔物。 之后，通过一个注入程序形成隔离区域，从而减少漏电流并简化工艺流程。

公开(公告)号：US5837426A

公开(公告)日：1998-11-17

申请号：US712406

申请日：1996-09-11

Applicant: Che-Pin Tseng ,  Wei-Jiang Lin ,  Wen-Cheng Tien ,  Yun-Kuei Yang

Inventor： Che-Pin Tseng ,  Wei-Jiang Lin ,  Wen-Cheng Tien ,  Yun-Kuei Yang

IPC: G03F7/20

CPC classification number: G03F7/70466 ,  G03F7/2022

Abstract: A photolithographic process which provides reduced line widths or reduced inter-element line spaces for the circuit elements on an IC chip, allowing the IC chip to have a higher degree of integration. The photolithographic process includes a double-exposure process on the same wafer defined by placing either the same photomask at two different positions or by using two photomasks. In the first exposure process, a first selected set of areas on the photoresist layer is exposed through the photomask. In the second exposure process, the photomask is shifted to predetermined positions interleaving or overlapping the positions where the first selected set of exposed areas are formed, or alternatively a second photomask replaces the first photomask. The second photomask has a plurality of patterns arranged in positions correspondingly interleaving or overlapping the positions where the first selected set of exposed areas is formed. The exposure light then illuminates the wafer again so as to expose a second selected set of areas on the photoresist layer. The first and second selected sets of exposed areas in combination constitute a layout for the circuit elements which are to be subsequently formed. Through the photolithographic process, the circuit elements are doubled in density compared with the corresponding patterns on the photomask and can be formed with a reduced line width or inter-element space.

Abstract translation: 为IC芯片上的电路元件提供减小的线宽或降低的元件间空间的光刻工艺，允许IC芯片具有更高的集成度。 光刻工艺包括在相同的晶片上的双曝光工艺，其通过将相同的光掩模放置在两个不同的位置或通过使用两个光掩模来定义。 在第一曝光过程中，光致抗蚀剂层上的第一选定区域通过光掩模曝光。 在第二曝光处理中，将光掩模移动到与形成第一所选曝光区域的位置交替或重叠的预定位置，或者替代地，第二光掩模替换第一光掩模。 第二光掩模具有布置在相应地交替或重叠形成第一所选曝光区域的位置的位置中的多个图案。 曝光光再次照亮晶片，以便露出光致抗蚀剂层上的第二选定区域。 组合的第一和第二选定的曝光区域组合构成随后形成的电路元件的布局。 通过光刻工艺，与光掩模上的相应图案相比，电路元件的密度加倍，并且可以以减小的线宽或元件间空间形成。