公开(公告)号：US5427970A

公开(公告)日：1995-06-27

申请号：US276604

申请日：1994-07-18

申请人： Chen-Chih Hsue ,  Gary Hong

发明人： Chen-Chih Hsue ,  Gary Hong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L29/66825 ,  H01L21/28141

摘要： A new method of fabricating a high coupling ratio Flash EEPROM memory cell is achieved. A layer of silicon dioxide is provided over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. The silicon dioxide layer not covered by the patterned silicon nitride layer is removed, thereby exposing portions of the substrate. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. Ions are implanted into the substrate using the silicon nitride layer and spacers as a mask to form implanted regions within the semiconductor substrate. The semiconductor substrate is oxidized where the implanted regions have been formed leaving the thin tunnel oxide only under the silicon nitride spacers. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer. The second polysilicon layer is patterned to form a control gate. Passivation and metallization complete the fabrication of the memory cell with improved coupling ratio.

摘要翻译： 实现了一种制造高耦合比闪存EEPROM存储单元的新方法。 在半导体衬底的表面上设置一层二氧化硅。 一层氮化硅沉积在二氧化硅层上并构图。 未被图案化氮化硅层覆盖的二氧化硅层被去除，从而暴露衬底的部分。 在半导体衬底的暴露部分上生长隧道氧化物层。 在图案化氮化硅层的侧壁上形成氮化硅间隔物。 使用氮化硅层和间隔物作为掩模将离子注入到衬底中，以在半导体衬底内形成注入区域。 半导体衬底被氧化，其中已经形成注入区域，仅在氮化硅间隔物之下留下薄的隧道氧化物。 去除氮化硅层和间隔物。 第一多晶硅层沉积在二氧化硅和隧道氧化物层的表面上并被图案化以形成浮栅。 在图案化的第一多晶硅层之后沉积多层介电层，随后是第二多晶硅层。 图案化第二多晶硅层以形成控制栅极。 钝化和金属化完成了具有改进的耦合比的存储器单元的制造。

公开(公告)号：US5434099A

公开(公告)日：1995-07-18

申请号：US270769

申请日：1994-07-05

申请人： Chen-Chih Hsue

发明人： Chen-Chih Hsue

IPC分类号： H01L21/762 ,  H01L27/092 ,  H01L21/76

CPC分类号： H01L21/76218 ,  H01L27/0928

摘要： The method requires fewer process steps. A nitride layer and a first overlying photoresist are deposited on a semiconductor substrate having wells of different impurity types. The resist layer is developed and to cover first type well and the device area of the opposite second type well. After the resultant exposed nitride layer is removed, impurity ions are implanted. The first photoresist layer is removed and a second photoresist layer deposited. The second resist layer is deposited and developed to cover the second well and the device area in the first well. The resultant exposed nitride areas are removed and ions implanted. The second photoresist layer is removed and the substrate oxidized to form field oxide regions. The nitride layer is removed and the substrate completed by forming devices, passivation layers and metallurgy.

摘要翻译： 该方法需要更少的处理步骤。 在具有不同杂质类型的阱的半导体衬底上沉积氮化物层和第一覆盖光致抗蚀剂。 抗蚀剂层被开发并覆盖第一类井和相对的第二类井的装置区域。 在除去所得到的暴露的氮化物层之后，注入杂质离子。 去除第一光致抗蚀剂层并沉积第二光致抗蚀剂层。 第二抗蚀剂层被沉积和显影以覆盖第一井中的第二井和装置区域。 去除所得到的暴露的氮化物区域并注入离子。 去除第二光致抗蚀剂层，并且底物被氧化以形成场氧化物区域。 去除氮化物层，并通过形成器件，钝化层和冶金来完成衬底。