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公开(公告)号：US20070083576A1
公开(公告)日：2007-04-12
申请号：US11246734
申请日：2005-10-08
申请人： Tien-Fu Chen , Chih-Heng Kang , Chen-Neng Win
发明人： Tien-Fu Chen , Chih-Heng Kang , Chen-Neng Win
IPC分类号： G06F15/00
CPC分类号： G06F9/30098 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/3016 , G06F9/30167 , G06F9/383
摘要： An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.
摘要翻译： 提供作为处理单元的组成部分的算术和逻辑器件以实现代码大小和开销降低。 算术和逻辑器件包含几个辅助计算单元，每个辅助计算单元在控制单元的控制下能够进行简单的算术和逻辑运算。 通过沿着数据路径配置辅助计算单元，可以在相同的指令周期内执行操作数的附加处理。 因此，结合这样的算术和逻辑器件的处理单元能够在代码尺寸和存储器访问开销方面实现显着的性能改进。
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2.发明授权Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle 有权Alu具有辅助单元，用于在相同指令周期内对操作数进行前后处理和即时值公开(公告)号：US07346761B2
公开(公告)日：2008-03-18
申请号：US11246734
申请日：2005-10-08
申请人： Tien-Fu Chen , Chih-Heng Kang , Chen-Neng Win
发明人： Tien-Fu Chen , Chih-Heng Kang , Chen-Neng Win
IPC分类号： G06F9/302
CPC分类号： G06F9/30098 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/3016 , G06F9/30167 , G06F9/383
摘要： An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.
摘要翻译： 提供作为处理单元的组成部分的算术和逻辑器件以实现代码大小和开销降低。 算术和逻辑器件包含几个辅助计算单元，每个辅助计算单元在控制单元的控制下能够进行简单的算术和逻辑运算。 通过沿着数据路径配置辅助计算单元，可以在相同的指令周期内执行操作数的附加处理。 因此，结合这样的算术和逻辑器件的处理单元能够在代码尺寸和存储器访问开销方面实现显着的性能改进。
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