公开(公告)号：US20050117668A1

公开(公告)日：2005-06-02

申请号：US10986086

申请日：2004-11-12

申请人： Cheng-Ming Tang ,  Wen-Tsai Liao

发明人： Cheng-Ming Tang ,  Wen-Tsai Liao

IPC分类号： H03M5/08 ,  H04L7/00 ,  H04L25/49 ,  H04L25/493 ,  H04L27/10

CPC分类号： H04L25/493 ,  H04L25/4906

摘要： The invention relates to a decoder for decoding a received signal to obtain a corresponding decoded bit series. The signal comprises a plurality of pulses. The decoder comprises a memory, a counting module, a transform module, and a logic module. The memory is for storing a predetermined look-up table; the look-up table comprises plural kinds of edge time duties and the corresponding decoded bit combinations thereof. The counting module is for measuring the edge time duty between high edges and low edges of adjacent pulses of the signal, so as to obtain a first and a second time series. The transform module, according to the look-up table, is for translating the first time series to a first decoded series, and the second time series to a second decoded series. The logic module is for performing a corresponding logic operation on the first and the second decoded series, so as to obtain the decoded bit series.

摘要翻译： 本发明涉及一种用于对接收信号进行解码以获得对应的解码比特序列的解码器。 信号包括多个脉冲。 解码器包括存储器，计数模块，变换模块和逻辑模块。 存储器用于存储预定的查找表; 查找表包括多种边缘时间任务及其对应的解码比特组合。 计数模块用于测量信号的相邻脉冲的高边缘和低边缘之间的边沿时间占空比，以获得第一和第二时间序列。 根据查找表，变换模块用于将第一时间序列转换为第一解码序列，将第二时间序列转换为第二解码序列。 逻辑模块用于对第一和第二解码序列执行对应的逻辑运算，以获得解码的比特序列。

公开(公告)号：US07081840B2

公开(公告)日：2006-07-25

申请号：US10986086

申请日：2004-11-12

申请人： Cheng-Ming Tang ,  Wen-Tsai Liao

发明人： Cheng-Ming Tang ,  Wen-Tsai Liao

IPC分类号： H03M1/10

CPC分类号： H04L25/493 ,  H04L25/4906

摘要： The invention relates to a decoder for decoding a received signal to obtain a corresponding decoded bit series. The signal comprises a plurality of pulses. The decoder comprises a memory, a counting module, a transform module, and a logic module. The memory is for storing a predetermined look-up table; the look-up table comprises plural kinds of edge time duties and the corresponding decoded bit combinations thereof. The counting module is for measuring the edge time duty between high edges and low edges of adjacent pulses of the signal, so as to obtain a first and a second time series. The transform module, according to the look-up table, is for translating the first time series to a first decoded series, and the second time series to a second decoded series. The logic module is for performing a corresponding logic operation on the first and the second decoded series, so as to obtain the decoded bit series.

摘要翻译： 本发明涉及一种用于对接收信号进行解码以获得对应的解码比特序列的解码器。 信号包括多个脉冲。 解码器包括存储器，计数模块，变换模块和逻辑模块。 存储器用于存储预定的查找表; 查找表包括多种边缘时间任务及其对应的解码比特组合。 计数模块用于测量信号的相邻脉冲的高边缘和低边缘之间的边沿时间占空比，以获得第一和第二时间序列。 根据查找表，变换模块用于将第一时间序列转换为第一解码序列，将第二时间序列转换为第二解码序列。 逻辑模块用于对第一和第二解码序列执行对应的逻辑运算，以获得解码的比特序列。