公开(公告)号：US20060190765A1

公开(公告)日：2006-08-24

申请号：US11344538

申请日：2006-01-30

Applicant: Nicolas Grossier ,  Chilakala Kumar ,  Saverio Pezzini

Inventor： Nicolas Grossier ,  Chilakala Kumar ,  Saverio Pezzini

IPC: G06F11/00

CPC classification number: G06F8/66 ,  G06F9/328

Abstract: A system for correcting errors in read-only memory devices by means of memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in the memory. The system includes a processing core, such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses being patched. The processing core is configured for providing different patch-data for correcting errors depending on whether it is performing a code access or a data access to an address being patched.

Abstract translation: 一种用于通过存储器补丁校正只读存储器件中的错误的系统，其中补丁数据被用作代替存储在存储器中给定位置的错误数据的读取数据。 该系统包括诸如ARM处理器的处理核心，其适于执行操作码访问以及对正在被修补的存储器地址的数据访问。 处理核心被配置用于根据其是执行代码访问还是对要修补的地址的数据访问来提供用于校正错误的不同补丁数据。