公开(公告)号：US20140118036A1

公开(公告)日：2014-05-01

申请号：US14105419

申请日：2013-12-13

申请人： Stefano Pietri ,  Chris C. Dao ,  Juxiang Ren ,  Nicolas Grossier ,  V. Srinivasan

发明人： Stefano Pietri ,  Chris C. Dao ,  Juxiang Ren ,  Nicolas Grossier ,  V. Srinivasan

IPC分类号： H03K17/22

CPC分类号： H03K17/22 ,  G01R31/2879 ,  G01R31/40

摘要： A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

摘要翻译： 一种用于控制集成电路装置的电压调节器的旁路的电压调节器旁路电路，所述电压调节器旁路电路包括第一电压检测器，第二电压检测器和电路。 第一电压检测器，用于检测核心电路电压电平高于第一阈值，并响应于检测在输出端断言第一检测信号。 第二电压检测器，用于检测未调节的电源电压高于第二阈值，并响应于检测在输出端断言第二检测信号。 电路具有耦合到第一电压检测器的输出端的第一输入端和耦合到第二电压检测器的输出端的第二输入端，该电路绕过电压调节器以响应锁存器的输出被清除。

公开(公告)号：US20060190765A1

公开(公告)日：2006-08-24

申请号：US11344538

申请日：2006-01-30

申请人： Nicolas Grossier ,  Chilakala Kumar ,  Saverio Pezzini

发明人： Nicolas Grossier ,  Chilakala Kumar ,  Saverio Pezzini

IPC分类号： G06F11/00

CPC分类号： G06F8/66 ,  G06F9/328

摘要： A system for correcting errors in read-only memory devices by means of memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in the memory. The system includes a processing core, such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses being patched. The processing core is configured for providing different patch-data for correcting errors depending on whether it is performing a code access or a data access to an address being patched.

摘要翻译： 一种用于通过存储器补丁校正只读存储器件中的错误的系统，其中补丁数据被用作代替存储在存储器中给定位置的错误数据的读取数据。 该系统包括诸如ARM处理器的处理核心，其适于执行操作码访问以及对正在被修补的存储器地址的数据访问。 处理核心被配置用于根据其是执行代码访问还是对要修补的地址的数据访问来提供用于校正错误的不同补丁数据。

公开(公告)号：US20130321071A1

公开(公告)日：2013-12-05

申请号：US13482271

申请日：2012-05-29

申请人： Stefano Pietri ,  Chris C. Dao ,  Juxiang Ren ,  Nicolas Grossier ,  V. Srinivasan

发明人： Stefano Pietri ,  Chris C. Dao ,  Juxiang Ren ,  Nicolas Grossier ,  V. Srinivasan

IPC分类号： G05F1/10

CPC分类号： H03K17/22 ,  G01R31/2879 ,  G01R31/40

摘要： A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

摘要翻译： 一种用于控制集成电路装置的电压调节器的旁路的电压调节器旁路电路，所述电压调节器旁路电路包括第一电压检测器，第二电压检测器和电路。 第一电压检测器，用于检测核心电路电压电平高于第一阈值，并响应于检测在输出端断言第一检测信号。 第二电压检测器，用于检测未调节的电源电压高于第二阈值，并响应于检测在输出端断言第二检测信号。 电路具有耦合到第一电压检测器的输出端的第一输入端和耦合到第二电压检测器的输出端的第二输入端，该电路绕过电压调节器以响应锁存器的输出被清除。

公开(公告)号：US09448811B2

公开(公告)日：2016-09-20

申请号：US14354005

申请日：2011-11-23

申请人： Carl Culshaw ,  Thomas Luedeke ,  Nicolas Grossier

发明人： Carl Culshaw ,  Thomas Luedeke ,  Nicolas Grossier

IPC分类号： G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/07

CPC分类号： G06F9/442 ,  G06F1/24 ,  G06F9/44505 ,  G06F11/0721 ,  G06F11/076

摘要： A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

摘要翻译： 微处理器设备包括至少一个复位管理模块。 所述至少一个复位管理模块被布置成检测包括第一复位电平的复位事件，确定在检测到包括第一复位电平的复位事件时是否满足了至少一个复位条件，并且引起第二复位的复位 确定已经满足至少一个复位条件。

公开(公告)号：US07143247B1

公开(公告)日：2006-11-28

申请号：US09563315

申请日：2000-05-02

申请人： Nicolas Grossier

发明人： Nicolas Grossier

IPC分类号： G06F12/00

CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3889

摘要： A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting onto the queue.

摘要翻译： 具有多个可以生成用于存储在存储器中的数据的并行执行管线的计算机系统可以在访问存储器之前将来自管线的数据存储在队列中，并且系统包括用于在插入到存储器之前从不同管道重新排序数据的电路 队列。

公开(公告)号：US06701425B1

公开(公告)日：2004-03-02

申请号：US09563153

申请日：2000-05-02

申请人： Ahmed Dabbagh ,  Nicolas Grossier ,  Bruno Bernard ,  Pierre-Yves Taloud

发明人： Ahmed Dabbagh ,  Nicolas Grossier ,  Bruno Bernard ,  Pierre-Yves Taloud

IPC分类号： G06F930

CPC分类号： G06F9/3834

摘要： A computer system with parallel execution pipelines and a memory access controller has store address queues holding addresses for store operations, store data queues holding a plurality of data for storing in the memory and load address storage holding addresses for load operations, said access controller including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits.

摘要翻译： 具有并行执行管线和存储器访问控制器的计算机系统具有保存用于存储操作的地址的存储地址队列，保存用于存储在存储器中的多个数据的存储数据队列和用于加载操作的加载地址存储保持地址，所述访问控制器包括比较器 用于将由控制器接收的负载地址与存储地址队列中的地址进行比较并且定位任何相同的地址的电路，每个所述地址包括表示字地址的第一组位与第二组字节使能位和所述 比较器具有用于比较两个地址的字节使能位以及所述第一组位的电路。

公开(公告)号：US08896370B2

公开(公告)日：2014-11-25

申请号：US14105419

申请日：2013-12-13

申请人： Stefano Pietri ,  Chris C. Dao ,  Juxiang Ren ,  Nicolas Grossier ,  V Srinivasan

发明人： Stefano Pietri ,  Chris C. Dao ,  Juxiang Ren ,  Nicolas Grossier ,  V Srinivasan

IPC分类号： G05F1/10 ,  G01R31/28 ,  H03K17/22 ,  G01R31/40

CPC分类号： H03K17/22 ,  G01R31/2879 ,  G01R31/40

摘要： A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

公开(公告)号：US06553478B1

公开(公告)日：2003-04-22

申请号：US09561629

申请日：2000-05-02

申请人： Nicolas Grossier

发明人： Nicolas Grossier

IPC分类号： G06F1200

CPC分类号： G06F12/0607

摘要： A memory for a computer system that includes a plurality of memory banks which provide an interleaved memory region as well as X and Y memory regions. Each memory access address includes a most significant set of bits indicating which of the interleaved, X, or Y memory regions is to be accessed. Each memory access address also includes a least significant set of bits indicating an address within the bank of the access region. At least one bit in the least significant set is a bank selector and one bit of the most significant set of bits is an X or Y region selector.

摘要翻译： 一种用于计算机系统的存储器，其包括提供交错存储器区域以及X和Y存储器区域的多个存储器组。 每个存储器访问地址包括指示交织的，X或Y存储器区域中的哪一个被访问的最高有效位。 每个存储器访问地址还包括指示访问区域的存储体内的地址的最低有效位。 最低有效集合中的至少一位是存储体选择器，最高有效位组的一位是X或Y区域选择器。

公开(公告)号：US20140298005A1

公开(公告)日：2014-10-02

申请号：US14354005

申请日：2011-11-23

申请人： Carl Culshaw ,  Thomas Luedeke ,  Nicolas Grossier

发明人： Carl Culshaw ,  Thomas Luedeke ,  Nicolas Grossier

IPC分类号： G06F9/445

CPC分类号： G06F9/442 ,  G06F1/24 ,  G06F9/44505 ,  G06F11/0721 ,  G06F11/076

摘要： A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

摘要翻译： 微处理器设备包括至少一个复位管理模块。 所述至少一个复位管理模块被布置成检测包括第一复位电平的复位事件，确定在检测到包括第一复位电平的复位事件时是否满足了至少一个复位条件，并且引起第二复位的复位 确定已经满足至少一个复位条件。

公开(公告)号：US20060190695A1

公开(公告)日：2006-08-24

申请号：US11344537

申请日：2006-01-30

申请人： Nicolas Grossier

发明人： Nicolas Grossier

IPC分类号： G06F12/14

CPC分类号： G06F9/30192 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3824 ,  G06F12/1491

摘要： A system for providing controlled access to a memory area storing code and data, includes a processor cooperating with the memory area. The processor is configured for marking the instructions processed with a field describing the origin of the code being executed, and enabling data access in the memory area only from authorized code. Typically, the processor includes a pipeline emulation block, and the controlled access to said memory area is implemented via the pipeline emulation block. The processor may be a RISC processor, such as an ARM processor, configured for associating with the instructions currently in the pipeline a bit marking if the instruction in question has been executed from an authorized memory area or not.

摘要翻译： 用于提供对存储代码和数据的存储区域的受控访问的系统包括与存储器区域协作的处理器。 处理器被配置为用描述正在执行的代码的原点的字段来标记处理的指令，并且仅允许来自授权代码的存储器区域中的数据访问。 通常，处理器包括流水线仿真块，并且经由流水线仿真块实现对所述存储器区域的受控访问。 处理器可以是诸如ARM处理器之类的RISC处理器，其被配置用于与当前在流水线中的指令相关联，如果所述指令是否已经从授权的存储区域执行，则该标记是位标记的。