公开(公告)号：US20060244477A1

公开(公告)日：2006-11-02

申请号：US11407941

申请日：2006-04-21

Applicant: Yao-Chi Wang ,  Ying-Tang Chang ,  Ching-Wen Pan ,  Chin-Pin Yu

Inventor： Yao-Chi Wang ,  Ying-Tang Chang ,  Ching-Wen Pan ,  Chin-Pin Yu

IPC: H03K19/003

CPC classification number: H03K19/00361

Abstract: A logic device with low electromagnetic interference. The logic device includes a digital logic gate, a voltage-limited circuit and a current-limited circuit. The digital logic gate provides a corresponding digital logic function. The voltage-limited circuit is connected to the digital logic gate in order to provide a fixed voltage to the digital logic gate to thus reduce an output voltage swing of the digital logic gate. The current-limited circuit is connected to the digital logic gate in order to provide a fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate. Accordingly, an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced with the reduced output voltage swing and transient current.

Abstract translation: 具有低电磁干扰的逻辑器件。 逻辑器件包括数字逻辑门，电压限制电路和限流电路。 数字逻辑门提供相应的数字逻辑功能。 电压限制电路连接到数字逻辑门，以便向数字逻辑门提供固定电压，从而降低数字逻辑门的输出电压摆幅。 电流限制电路连接到数字逻辑门，以便向数字逻辑门提供固定电流，从而减少数字逻辑门的瞬态电流。 因此，由于数字逻辑门的切换引起的电磁接口（EMI）随着输出电压摆幅和瞬态电流的降低而降低。

公开(公告)号：US07362141B2

公开(公告)日：2008-04-22

申请号：US11407941

申请日：2006-04-21

Applicant: Yao-Chi Wang ,  Ying-Tang Chang ,  Ching-Wen Pan ,  Chin-Pin Yu

Inventor： Yao-Chi Wang ,  Ying-Tang Chang ,  Ching-Wen Pan ,  Chin-Pin Yu

IPC: H03F3/45

CPC classification number: H03K19/00361

Abstract: A logic device with low electromagnetic interference. The logic device includes a digital logic gate, a voltage-limited circuit and a current-limited circuit. The digital logic gate provides a corresponding digital logic function. The voltage-limited circuit is connected to the digital logic gate in order to provide a fixed voltage to the digital logic gate to thus reduce an output voltage swing of the digital logic gate. The current-limited circuit is connected to the digital logic gate in order to provide a fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate. Accordingly, an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced with the reduced output voltage swing and transient current.

Abstract translation: 具有低电磁干扰的逻辑器件。 逻辑器件包括数字逻辑门，电压限制电路和限流电路。 数字逻辑门提供相应的数字逻辑功能。 电压限制电路连接到数字逻辑门，以便向数字逻辑门提供固定电压，从而降低数字逻辑门的输出电压摆幅。 电流限制电路连接到数字逻辑门，以便向数字逻辑门提供固定电流，从而减少数字逻辑门的瞬态电流。 因此，由于数字逻辑门的切换引起的电磁接口（EMI）随着输出电压摆幅和瞬态电流的降低而降低。