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    SYNCHRONIZING TIMING MISMATCH BY DATA INSERTION
    1.
    发明申请
    SYNCHRONIZING TIMING MISMATCH BY DATA INSERTION 有权
    通过数据插入同步时序错误

    公开(公告)号：US20090259671A1

    公开(公告)日：2009-10-15

    申请号：US12118469

    申请日：2008-05-09

    申请人： Harinath Garudadri ,  Somdeb Majumdar ,  Rouzbeh Kashef ,  Chinnappa K. Ganapathy

    发明人： Harinath Garudadri ,  Somdeb Majumdar ,  Rouzbeh Kashef ,  Chinnappa K. Ganapathy

    IPC分类号： G06F17/30

    CPC分类号： H04L7/0016 ,  G10L19/005 ,  H04L7/0029 ,  H04L7/005 ,  H04L25/05

    摘要： The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a transmit clock while a receiving device that receives the transmitted data may process the data according to a receive clock. If there is a timing mismatch between the transmit and receive clocks, the receiving device may receive data faster or slower than it processes the data. In such a case, there may be errors relating to the processing of the received data. To address timing mismatches such as this, the receiving device may delete data from or insert data into the received data. In conjunction with these operations, the receiving device may modify the received data at or near the insertion point or the deletion point in a manner that mitigates any adverse effect the insertion or deletion may have on a resulting output signal.

    摘要翻译： 一个设备提供数据的速率和另一个设备处理该数据的速率可能不同。 例如，发送装置可以根据发送时钟发送数据，而接收发送的数据的接收装置可以根据接收时钟处理数据。 如果在发送和接收时钟之间存在定时不匹配，则接收设备可能比处理数据更快或更慢地接收数据。 在这种情况下，可能存在与接收到的数据的处理有关的错误。 为了解决诸如此的定时不匹配，接收设备可以从接收到的数据中删除数据或将数据插入到数据中。 结合这些操作，接收设备可以以减轻插入或删除对结果输出信号可能产生的任何不利影响的方式在插入点或删除点处或附近修改接收到的数据。

    METHOD AND APPARATUS FOR INTEGRATED CLOCK MISMATCH COMPENSATION AND PACKET LOSS CONCEALMENT
    2.
    发明申请
    METHOD AND APPARATUS FOR INTEGRATED CLOCK MISMATCH COMPENSATION AND PACKET LOSS CONCEALMENT 审中-公开
    集成时钟误差补偿和分组丢失隐藏的方法和装置

    公开(公告)号：US20100080331A1

    公开(公告)日：2010-04-01

    申请号：US12365357

    申请日：2009-02-04

    申请人： Harinath Garudadri ,  Rouzbeh Kashef ,  Somdeb Majumdar ,  Chinnappa K. Ganapathy

    发明人： Harinath Garudadri ,  Rouzbeh Kashef ,  Somdeb Majumdar ,  Chinnappa K. Ganapathy

    IPC分类号： H04L7/00

    CPC分类号： H04J3/0632 ,  H04L7/005 ,  H04L12/6418

    摘要： An apparatus and method for processing data are disclosed. The apparatus may include a receiver clock, and a processing system configured to use the receiver clock to receive data from a transmitter, the data being generated with a transmitter clock in the transmitter, wherein the processing system is further configured to estimate a mismatch between the transmitter and receiver clocks, and to determine whether to modify the data based on the estimated mismatch.

    摘要翻译： 公开了一种用于处理数据的装置和方法。 所述设备可以包括接收器时钟，以及被配置为使用所述接收机时钟从所述发射机接收数据的处理系统，所述数据是利用所述发射机中的发射机时钟生成的，其中所述处理系统还被配置为： 发射机和接收机时钟，并且基于估计的不匹配来确定是否修改数据。

    IFFT PROCESSING IN WIRELESS COMMUNICATIONS
    3.
    发明申请
    IFFT PROCESSING IN WIRELESS COMMUNICATIONS 有权
    无线通信中的IFFT处理

    公开(公告)号：US20080040413A1

    公开(公告)日：2008-02-14

    申请号：US11612456

    申请日：2006-12-18

    申请人： Jai N. Subrahmanyam ,  Chinnappa K. Ganapathy ,  Durk L. van Veen ,  Jinxia Bai ,  Kevin S. Cousineau ,  Seokyong Oh

    发明人： Jai N. Subrahmanyam ,  Chinnappa K. Ganapathy ,  Durk L. van Veen ,  Jinxia Bai ,  Kevin S. Cousineau ,  Seokyong Oh

    IPC分类号： G06F15/00

    CPC分类号： H04L27/2626

    摘要： Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

    摘要翻译： 描述了用于执行IFFT流水线的技术。 在一些方面，流水线通过具有具有第一和第二部分的存储器的处理系统来实现，编码器被配置为处理第一和第二存储器部分中的每一个中的数据;被配置为处理第一和第二部分中的编码数据的IFFT 存储器部分和后处理器，其被配置为在IFFT处理第二存储器部分中的编码数据时处理第一存储器部分中的IFFT处理的数据，后处理器被配置为以与编码器不同的时钟速度操作 IFFT。

    IFFT processing in wireless communications
    5.
    发明授权
    IFFT processing in wireless communications 有权
    无线通信中的IFFT处理

    公开(公告)号：US08612504B2

    公开(公告)日：2013-12-17

    申请号：US11612456

    申请日：2006-12-18

    申请人： Jai N. Subrahmanyam ,  Chinnappa K. Ganapathy ,  Durk L. Van Veen ,  Jinxia Bai ,  Kevin S. Cousineau ,  Seokyong Oh

    发明人： Jai N. Subrahmanyam ,  Chinnappa K. Ganapathy ,  Durk L. Van Veen ,  Jinxia Bai ,  Kevin S. Cousineau ,  Seokyong Oh

    IPC分类号： G06F17/14 ,  G06F15/00

    CPC分类号： H04L27/2626

    摘要： Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

    摘要翻译： 描述了执行IFFT流水线技术。 在一些方面，流水线通过具有具有第一和第二部分的存储器的处理系统来实现，编码器被配置为处理第一和第二存储器部分中的每一个中的数据;被配置为处理第一和第二部分中的编码数据的IFFT 存储器部分和后处理器，其被配置为在IFFT处理第二存储器部分中的编码数据时处理第一存储器部分中的IFFT处理的数据，后处理器被配置为以与编码器不同的时钟速度操作 IFFT。

    Synchronizing timing mismatch by data insertion
    6.
    发明授权
    Synchronizing timing mismatch by data insertion 有权
    通过数据插入同步定时不匹配

    公开(公告)号：US08589720B2

    公开(公告)日：2013-11-19

    申请号：US12118469

    申请日：2008-05-09

    申请人： Harinath Garudadri ,  Somdeb Majumdar ,  Rouzbeh Kashef ,  Chinnappa K. Ganapathy

    发明人： Harinath Garudadri ,  Somdeb Majumdar ,  Rouzbeh Kashef ,  Chinnappa K. Ganapathy

    IPC分类号： G06F1/04

    CPC分类号： H04L7/0016 ,  G10L19/005 ,  H04L7/0029 ,  H04L7/005 ,  H04L25/05

    摘要： The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a transmit clock while a receiving device that receives the transmitted data may process the data according to a receive clock. If there is a timing mismatch between the transmit and receive clocks, the receiving device may receive data faster or slower than it processes the data. In such a case, there may be errors relating to the processing of the received data. To address timing mismatches such as this, the receiving device may delete data from or insert data into the received data. In conjunction with these operations, the receiving device may modify the received data at or near the insertion point or the deletion point in a manner that mitigates any adverse effect the insertion or deletion may have on a resulting output signal.

    摘要翻译： 一个设备提供数据的速率和另一个设备处理该数据的速率可能不同。 例如，发送装置可以根据发送时钟发送数据，而接收发送的数据的接收装置可以根据接收时钟处理数据。 如果在发送和接收时钟之间存在定时不匹配，则接收设备可能比处理数据更快或更慢地接收数据。 在这种情况下，可能存在与接收到的数据的处理有关的错误。 为了解决诸如此的定时不匹配，接收设备可以从接收到的数据中删除数据或将数据插入到数据中。 结合这些操作，接收设备可以以减轻插入或删除对结果输出信号可能产生的任何不利影响的方式在插入点或删除点处或附近修改接收到的数据。

    Apparatus and methods for control of sleep modes in a transceiver
    7.
    发明授权
    Apparatus and methods for control of sleep modes in a transceiver 有权
    用于控制收发器中睡眠模式的装置和方法

    公开(公告)号：US08509859B2

    公开(公告)日：2013-08-13

    申请号：US11372876

    申请日：2006-03-10

    申请人： Tadeusz Jarosinski ,  Chinnappa K. Ganapathy ,  Michael Mao Wang

    发明人： Tadeusz Jarosinski ,  Chinnappa K. Ganapathy ,  Michael Mao Wang

    IPC分类号： H04B1/16 ,  H04B1/38 ,  H04M1/00

    CPC分类号： H04W52/0225 ,  H04B1/1615 ,  H04W52/0293 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/164 ,  Y02D70/40

    摘要： Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

    摘要翻译： 公开了用于在收发器或接收器中控制睡眠模式的装置和方法。 具体地，公开了一种收发器，其包括被配置为确定关于收发器内的部件的至少一部分的睡眠周期的定时信息的处理器。 收发器还包括耦合到处理器的睡眠控制逻辑，以从处理器接收关于睡眠周期的信息，并且被配置为在与处理器无关的功率衰减周期期间实现收发器的至少一部分组件的关闭。

    Channel decoding-based error detection
    8.
    发明授权
    Channel decoding-based error detection 有权
    基于信道解码的错误检测

    公开(公告)号：US08423852B2

    公开(公告)日：2013-04-16

    申请号：US12146301

    申请日：2008-06-25

    申请人： Harinath Garudadri ,  Somdeb Majumdar ,  David Jonathan Julian ,  Chinnappa K. Ganapathy

    发明人： Harinath Garudadri ,  Somdeb Majumdar ,  David Jonathan Julian ,  Chinnappa K. Ganapathy

    IPC分类号： H04L1/00 ,  G06F11/00

    CPC分类号： H04L1/0045 ,  G10L19/005 ,  H04L1/0057

    摘要： Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits. In some aspects a set of data including at least one bit in error may be replaced with data that is generated by performing linear interpolation operations on PCM equivalent data that is associated with neighboring data sets.

    摘要翻译： 可以采用低延迟和计算有效的技术来解决数据中的错误，例如低位宽度，过采样数据。 在一些方面，可以采用这些技术来减轻与Σ-Δ调制音频数据相关联的音频伪影。 在一些方面，可以基于信道解码过程的结果在一组编码数据中检测到错误。 在确定一组数据可能包含至少一个错误时，可以用基于一个或多个相邻数据集的另一组数据替换该数据集。 例如，在一些方面，包括至少一个错误位的一组数据可以由通过对相邻数据集应用交叉衰落操作而产生的数据代替。 在一些方面，作为施加到与给定数据位及其相邻数据位相关联的PCM等效数据的线性预测操作的结果，可以翻转给定数据位。 在一些方面，包括至少一个错误位的一组数据可以由通过对与相邻数据集相关联的PCM等效数据执行线性内插操作而产生的数据代替。

    Methods and apparatus for dynamic packet mapping
    9.
    发明授权
    Methods and apparatus for dynamic packet mapping 有权
    动态分组映射的方法和装置

    公开(公告)号：US08139612B2

    公开(公告)日：2012-03-20

    申请号：US11398156

    申请日：2006-04-04

    申请人： Jinxia Bai ,  Chinnappa K. Ganapathy ,  Thomas Sun

    发明人： Jinxia Bai ,  Chinnappa K. Ganapathy ,  Thomas Sun

    IPC分类号： H04J13/00 ,  H04J9/00 ,  H04J11/00 ,  H04J1/00

    CPC分类号： H04N21/434 ,  H04L27/2647 ,  H04L49/9078 ,  H04W8/26 ,  H04W28/14

    摘要： Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.

    摘要翻译： 动态分组映射的方法和装置。 提供了一种用于映射度量数据以产生与信道相关联的可解码分组的方法。 该方法包括获取与度量数据相关联的信道标识符，基于信道标识确定来自多个缓冲器的可用缓冲器，将度量数据写入可用缓冲器，检测何时在多个选定缓冲器中形成可解码分组 并且从所选择的缓冲器输出可解码分组。 一种装置包括多个缓冲器和映射逻辑，其被配置为获得与度量数据相关联的信道标识符，基于信道标识确定可用缓冲器，将度量数据写入可用缓冲器，检测何时形成可解码分组 选择的缓冲器，并从所选缓冲器输出可解码分组。