公开(公告)号：US07728807B2

公开(公告)日：2010-06-01

申请号：US11344899

申请日：2006-02-01

申请人： Chor Yin Chia

发明人： Chor Yin Chia

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G2320/0673

摘要： Techniques are provided for producing two output voltages that are substantially symmetric about a middle voltage (VCOM), based on a digital data value stored in a register. A first output voltage is produced based on the digital data value stored in the register. Additionally, the digital data value stored in the register is converted (e.g., by determining its 2's compliment) to a second digital data value, which is used to produce a second output voltage that is substantially symmetric about VCOM with the first output voltage. Alternatively, the digital data value stored in the register is provided to two different DACs that have their pair of reference voltages swapped (where the reference voltages are symmetric about VCOM), which will result in the outputs of the DACs being substantially symmetric about VCOM.

摘要翻译： 基于存储在寄存器中的数字数据值，提供了用于产生基于中间电压（VCOM）基本对称的两个输出电压的技术。 基于存储在寄存器中的数字数据值产生第一输出电压。 此外，存储在寄存器中的数字数据值被转换（例如，通过确定其2的补码）到第二数字数据值，该第二数字数据值用于产生具有第一输出电压的关于VCOM基本对称的第二输出电压。 或者，存储在寄存器中的数字数据值被提供给两个不同的DAC，它们具有交换的参考电压对（其中参考电压关于VCOM对称），这将导致DAC的输出基本对称关于VCOM。

公开(公告)号：US07193551B2

公开(公告)日：2007-03-20

申请号：US11207480

申请日：2005-08-19

申请人： Chor Yin Chia

发明人： Chor Yin Chia

IPC分类号： H03M1/66

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G2320/0673

摘要： A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

摘要翻译： 多参考电压发生器包括接口控制器，N个m位寄存器的第一组和N个m位寄存器的第二组。 第一多路复用器具有连接到第一和第二组寄存器的输出的输入。 m位数模（DAC）具有连接到第一多路复用器的输出的m位并行输入。 模拟解复用器具有连接到m位DAC的模拟输出的输入。 第一组N个采样保持（S / H）电路中的每个采样和保持电路连接到模拟解复用器的相应输出端。 类似地，第二组N S / H电路中的每个S / H电路连接到模拟解复用器的相应输出。 N个进一步的多路复用器各自具有连接到第一组中的对应的一个S / H电路的输出的第一输入和连接到第二组中的对应的一个S / H电路的输出的第二输入。 N个输出缓冲器各自具有连接到N个进一步多路复用器中的相应一个的输出的输入和用于驱动列驱动器的输出。

公开(公告)号：US08115755B2

公开(公告)日：2012-02-14

申请号：US11609853

申请日：2006-12-12

申请人： Chor-Yin Chia

发明人： Chor-Yin Chia

IPC分类号： G06F3/038 ,  G09G5/00

CPC分类号： G09G3/3611 ,  G06F1/3203 ,  G06F1/3265 ,  G09G3/3685 ,  G09G5/399 ,  G09G2320/103 ,  G09G2330/021 ,  Y02D10/153

摘要： Provided herein are methods and configurations for use with systems that drive or otherwise control displays (e.g., LCD displays). Such systems often include devices (e.g., buffers, DACs, ADCs, etc.) that require a sufficiently high bias current to enable the device to have a sufficiently fast slew rate and settling time, which may consume an undesirable high amount of power. Embodiments of the present invention adjust such bias current to reduce power consumption. A first bias current level is provided to the device when an input to, and a corresponding output from, the device are to transition from one level to another. A second bias current level is provided to the device when the input to, and the corresponding output from, the device are not to transition from one level to another, where the second bias current level is lower than the first bias current level.

摘要翻译： 本文提供了用于驱动或以其它方式控制显示器（例如，LCD显示器）的系统的方法和配置。 这样的系统通常包括需要足够高的偏置电流的器件（例如，缓冲器，DAC，ADC等），以使器件能够具有足够快的转换速率和稳定时间，这可能消耗不期望的大量功率。 本发明的实施例调整这种偏置电流以降低功耗。 当设备的输入和相应的输出从一个电平转换到另一个电平时，向器件提供第一偏置电流电平。 当第二偏置电流电平低于第一偏置电流电平时，第二偏置电流电平被提供给器件，当器件的输入和相应的器件输出不从一个电平转变到另一个电平时。

公开(公告)号：US20110273430A1

公开(公告)日：2011-11-10

申请号：US13021623

申请日：2011-02-04

申请人： Chor Yin Chia ,  Hong Joong Kim

发明人： Chor Yin Chia ,  Hong Joong Kim

IPC分类号： G06F3/038 ,  H03L5/00

CPC分类号： G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0289 ,  G09G2330/021

摘要： In an embodiment, a voltage level shifter circuit includes a first terminal configured to be connected to a high voltage supply rail (Vs+), a second terminal configured to be connected to a low voltage supply rail (Vs−), and an output voltage (VOUT) terminal. The voltage level shifter can also include a compensation voltage (VCOMP) node. Additionally, the voltage level shifter includes a plurality of switches configurable in a plurality of configurations, and control circuitry configured to control the switches so that in at least one of the configurations a load connected to the output voltage (VOUT) terminal does not draw any power from the low voltage supply rail (Vs−) and the high voltage supply rail (Vs+). The load can be, e.g., a gate drive circuit of a display panel, such as a thin film transistor-liquid crystal display (TFT-LCD) panel, but is not limited thereto.

摘要翻译： 在一个实施例中，电压电平移位器电路包括被配置为连接到高电压电源轨（Vs +）的第一端子，被配置为连接到低电压电源轨（Vs-）的第二端子和输出电压 VOUT）端子。 电压电平移位器还可以包括补偿电压（VCOMP）节点。 此外，电压电平移位器包括可配置为多个配置的多个开关，以及被配置为控制开关的控制电路，使得在至少一个配置中，连接到输出电压（VOUT）端子的负载不绘制任何 来自低压电源轨（Vs-）和高压电源轨（Vs +）的电力。 负载可以是例如显示面板的栅极驱动电路，例如薄膜晶体管 - 液晶显示器（TFT-LCD）面板，但不限于此。

公开(公告)号：US20080079706A1

公开(公告)日：2008-04-03

申请号：US11609853

申请日：2006-12-12

申请人： Chor-Yin Chia

发明人： Chor-Yin Chia

IPC分类号： G06F3/038

CPC分类号： G09G3/3611 ,  G06F1/3203 ,  G06F1/3265 ,  G09G3/3685 ,  G09G5/399 ,  G09G2320/103 ,  G09G2330/021 ,  Y02D10/153

摘要： Provided herein are methods and configurations for use with systems that drive or otherwise control displays (e.g., LCD displays). Such systems often include devices (e.g., buffers, DACs, ADCs, etc.) that require a sufficiently high bias current to enable the device to have a sufficiently fast slew rate and settling time, which may consume an undesirable high amount of power. Embodiments of the present invention adjust such bias current to reduce power consumption. A first bias current level is provided to the device when an input to, and a corresponding output from, the device are to transition from one level to another. A second bias current level is provided to the device when the input to, and the corresponding output from, the device are not to transition from one level to another, where the second bias current level is lower than the first bias current level.

摘要翻译： 本文提供了用于驱动或以其他方式控制显示器（例如，LCD显示器）的系统的方法和配置。 这样的系统通常包括需要足够高的偏置电流的器件（例如，缓冲器，DAC，ADC等），以使器件能够具有足够快的转换速率和稳定时间，这可能消耗不期望的大量功率。 本发明的实施例调整这种偏置电流以降低功耗。 当设备的输入和相应的输出从一个电平转换到另一个电平时，向器件提供第一偏置电流电平。 当第二偏置电流电平低于第一偏置电流电平时，第二偏置电流电平被提供给器件，当器件的输入和相应的器件输出不从一个电平转变到另一个电平时。

公开(公告)号：US07907109B2

公开(公告)日：2011-03-15

申请号：US11540698

申请日：2006-09-29

申请人： Chor Yin Chia

发明人： Chor Yin Chia

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G2320/0673

摘要： A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

摘要翻译： 多参考电压发生器包括接口控制器，N个m位寄存器的第一组和N个m位寄存器的第二组。 第一多路复用器具有连接到第一和第二组寄存器的输出的输入。 m位数模（DAC）具有连接到第一多路复用器的输出的m位并行输入。 模拟解复用器具有连接到m位DAC的模拟输出的输入。 第一组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 类似地，第二组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 N个进一步的多路复用器各自具有连接到第一组中的相应一个电压存储装置的输出的第一输入和连接到第二组中的对应的一个电压存储装置的输出的第二输入。 N个输出缓冲器各自具有连接到N个进一步多路复用器中的相应一个的输出的输入和用于驱动列驱动器的输出。

公开(公告)号：US20070018936A1

公开(公告)日：2007-01-25

申请号：US11540698

申请日：2006-09-29

申请人： Chor Yin Chia

发明人： Chor Yin Chia

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G2320/0673

摘要： A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

摘要翻译： 多参考电压发生器包括接口控制器，N个m位寄存器的第一组和N个m位寄存器的第二组。 第一多路复用器具有连接到第一和第二组寄存器的输出的输入。 m位数模（DAC）具有连接到第一多路复用器的输出的m位并行输入。 模拟解复用器具有连接到m位DAC的模拟输出的输入。 第一组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 类似地，第二组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 N个进一步的多路复用器各自具有连接到第一组中的相应一个电压存储装置的输出的第一输入和连接到第二组中的对应的一个电压存储装置的输出的第二输入。 N个输出缓冲器各自具有连接到N个进一步多路复用器中的相应一个的输出的输入和用于驱动列驱动器的输出。

公开(公告)号：US06897800B2

公开(公告)日：2005-05-24

申请号：US10236340

申请日：2002-09-05

申请人： Chor-Yin Chia

发明人： Chor-Yin Chia

IPC分类号： H03F3/72 ,  H03K17/00 ,  H03K17/16 ,  H03K17/693 ,  H03M1/12

CPC分类号： H03K17/007 ,  H03K17/162 ,  H03K17/693

摘要： The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1-AMPN). The output and inverting (−) input of amplifiers (AMP1-AMPN) are connected by a respective capacitor (C1-CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1-AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1-AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1-AMPN) through (A1), the gain and any offset of (AMP1-AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2). In operation, switches (S40, S50, S30 and S35) are initially closed, while switches (S2a, S2b, etc.) are open to charge both capacitors (CS1) and (CS2) and the inputs and output of (A1) to (VREF). Switch (S50) provides feedback to divide down gain errors and offset of (A1). Switches (S30, S35, S40 and S50) are then open, while one of switches (S2a, S2b, etc.) is closed with one switch (S1a, S1b, etc) to drive one of the output voltages (VOUT1-VOUTN). With inputs and outputs of (A1) and the connected (AMP1-AMPN) initially be at (VREF), very little settling time is needed.

公开(公告)号：US08384650B2

公开(公告)日：2013-02-26

申请号：US13019558

申请日：2011-02-02

申请人： Chor Yin Chia

发明人： Chor Yin Chia

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G2320/0673

摘要： A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

摘要翻译： 多参考电压发生器包括接口控制器，N个m位寄存器的第一组和N个m位寄存器的第二组。 第一多路复用器具有连接到第一和第二组寄存器的输出的输入。 m位数模（DAC）具有连接到第一多路复用器的输出的m位并行输入。 模拟解复用器具有连接到m位DAC的模拟输出的输入。 第一组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 类似地，第二组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 N个进一步的多路复用器各自具有连接到第一组中的相应一个电压存储装置的输出的第一输入和连接到第二组中的对应的一个电压存储装置的输出的第二输入。 N个输出缓冲器各自具有连接到N个进一步多路复用器中的相应一个的输出的输入和用于驱动列驱动器的输出。

公开(公告)号：US20110122056A1

公开(公告)日：2011-05-26

申请号：US13019558

申请日：2011-02-02

申请人： Chor Yin Chia

发明人： Chor Yin Chia

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G2320/0673

摘要： A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

摘要翻译： 多参考电压发生器包括接口控制器，N个m位寄存器的第一组和N个m位寄存器的第二组。 第一多路复用器具有连接到第一和第二组寄存器的输出的输入。 m位数模（DAC）具有连接到第一多路复用器的输出的m位并行输入。 模拟解复用器具有连接到m位DAC的模拟输出的输入。 第一组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 类似地，第二组N个电压存储装置中的每个电压存储装置连接到模拟解复用器的相应输出端。 N个进一步的多路复用器各自具有连接到第一组中的相应一个电压存储装置的输出的第一输入和连接到第二组中的对应的一个电压存储装置的输出的第二输入。 N个输出缓冲器各自具有连接到N个进一步多路复用器中的相应一个的输出的输入和用于驱动列驱动器的输出。