公开(公告)号：US07324183B2

公开(公告)日：2008-01-29

申请号：US10906891

申请日：2005-03-11

Applicant: Chun-Lin Wu ,  Kai-Yuan Ho ,  Chau-Chi Shen ,  Ren-Jie Chen

Inventor： Chun-Lin Wu ,  Kai-Yuan Ho ,  Chau-Chi Shen ,  Ren-Jie Chen

IPC: G02F1/1343 ,  G02F1/1333 ,  G02F1/136

CPC classification number: G02F1/136213 ,  G02F1/136259

Abstract: A thin film transistor array substrate and repairing methods thereof are disclosed. The thin film transistor array substrate comprises openings in each pixel electrode, each capacitor electrode and each common line. The openings of the capacitor electrode and the common line are located in the opening of the pixel electrode. The opening of the capacitor electrode exposes a portion area of the capacitor electrode and the common line. The pixel electrode is coupled to the common line through a connecting conductive layer. The MII storage capacitor Cst is formed by the pixel electrode and the capacitor electrode. When the MII storage capacitor Cst fails, the MII storage capacitor Cst can be switched to the MIM storage capacitor Cst by laser repairing.

Abstract translation: 公开了一种薄膜晶体管阵列基板及其修复方法。 薄膜晶体管阵列基板包括每个像素电极中的开口，每个电容器电极和每条公共线。 电容器电极和公共线的开口位于像素电极的开口中。 电容器电极的开口暴露电容器电极和公共线的部分区域。 像素电极通过连接导电层耦合到公共线。 MII存储电容器Cst由像素电极和电容器电极形成。 当MII存储电容器Cst失效时，MII存储电容器Cst可以通过激光修复切换到MIM存储电容器Cst。

公开(公告)号：US20060012726A1

公开(公告)日：2006-01-19

申请号：US10906891

申请日：2005-03-11

Applicant: Chun-Lin Wu ,  Kai-Yuan Ho ,  Chau-Chi Shen ,  Ren-Jie Chen

Inventor： Chun-Lin Wu ,  Kai-Yuan Ho ,  Chau-Chi Shen ,  Ren-Jie Chen

IPC: G02F1/136

CPC classification number: G02F1/136213 ,  G02F1/136259

Abstract: A thin film transistor array substrate and repairing methods thereof are disclosed. The thin film transistor array substrate comprises openings in each pixel electrode, each capacitor electrode and each common line. The openings of the capacitor electrode and the common line are located in the opening of the pixel electrode. The opening of the capacitor electrode exposes a portion area of the capacitor electrode and the common line. The pixel electrode is coupled to the common line through a connecting conductive layer. The MII storage capacitor Cst is formed by the pixel electrode and the capacitor electrode. When the MII storage capacitor Cst fails, the MII storage capacitor Cst can be switched to the MIM storage capacitor Cst by laser repairing.

Abstract translation: 公开了一种薄膜晶体管阵列基板及其修复方法。 薄膜晶体管阵列基板包括每个像素电极中的开口，每个电容器电极和每条公共线。 电容器电极和公共线的开口位于像素电极的开口中。 电容器电极的开口暴露电容器电极和公共线的部分区域。 像素电极通过连接导电层耦合到公共线。 MII存储电容器Cst由像素电极和电容器电极形成。 当MII存储电容器Cst失效时，MII存储电容器Cst可以通过激光修复切换到MIM存储电容器Cst。

公开(公告)号：US06864109B2

公开(公告)日：2005-03-08

申请号：US10625410

申请日：2003-07-23

Applicant: Vincent S. Chang ,  Chi-Chun Chen ,  Chun-Lin Wu ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Vincent S. Chang ,  Chi-Chun Chen ,  Chun-Lin Wu ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: G01N21/71 ,  H01L21/314 ,  H01L29/78 ,  H01L21/26 ,  H01L21/66

CPC classification number: H01J37/32935 ,  G01N21/71 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/7833

Abstract: A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analysing the in intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.

Abstract translation: 一种确定集成电路特征的组成的方法，包括收集表示在等离子体中等离子体产生的辐射能的光谱波长的强度数据，所述等离子体在等离子体氮化期间设置在基板上的集成电路特征，分析强度数据以确定峰强度 在一个波长处，并且基于峰值强度确定特征的分量浓度。

公开(公告)号：US20050019964A1

公开(公告)日：2005-01-27

申请号：US10625410

申请日：2003-07-23

Applicant: Vincent Chang ,  Chi-Chun Chen ,  Chun-Lin Wu ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Vincent Chang ,  Chi-Chun Chen ,  Chun-Lin Wu ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: G01N21/71 ,  H01L21/314 ,  H01L29/78 ,  H01L21/66

CPC classification number: H01J37/32935 ,  G01N21/71 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/7833

Abstract: A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analyzing the intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.

Abstract translation: 一种确定集成电路特征的组成的方法，包括收集表示在等离子体中等离子体产生的辐射能的光谱波长的强度数据，所述等离子体在等离子体氮化期间设置在衬底上的集成电路特征，分析强度数据以确定峰强度 一个波长，并且基于峰值强度确定特征的分量浓度。

公开(公告)号：US06737362B1

公开(公告)日：2004-05-18

申请号：US10377568

申请日：2003-02-28

Applicant: Chia Lin Chen ,  Chun-Lin Wu ,  Chi-Chun Chen ,  Tze Liang Lee ,  Shih-Chang Chen

Inventor： Chia Lin Chen ,  Chun-Lin Wu ,  Chi-Chun Chen ,  Tze Liang Lee ,  Shih-Chang Chen

IPC: H01L213105

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: The present disclosure provides a method for forming a gate stack structure for semiconductor devices. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness using a diluted etchant; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.

Abstract translation: 本公开提供了一种用于形成半导体器件的栅极堆叠结构的方法。 所公开的方法包括在衬底上形成介电层的步骤; 在形成的介电层上施加等离子体氮化处理; 在沉积的介电层上施加第一退火工艺; 使用稀释的蚀刻剂将介电层蚀刻到预定厚度; 在蚀刻后在蚀刻的电介质层上使用氧气环境进行第二退火处理; 以及在所述电介质层的顶部上形成栅电极层。 蚀刻使得蚀刻的电介质层的顶部具有比蚀刻的电介质层的下部显着更高的氮浓度，因此泄漏电流显着降低。