公开(公告)号：US20240355668A1

公开(公告)日：2024-10-24

申请号：US18637949

申请日：2024-04-17

申请人： CANON MEDICAL SYSTEMS CORPORATION

发明人： Tatsuya SUZUKI ,  Nobuhiko SATO

IPC分类号： H01L21/70 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234

CPC分类号： H01L21/707 ,  H01L21/0214 ,  H01L21/0228 ,  H01L21/28202 ,  H01L21/823475

摘要： A semiconductor apparatus according to an embodiment of the present disclosure includes: a substrate; a wiring layer serving as a topmost layer formed over the substrate; a first protection film formed so as to cover the wiring layer; a planarization film formed on the first protection film; and a second protection film formed on the planarization film. The first protection film and the second protection film are each thicker than the planarization film.

公开(公告)号：US12009409B2

公开(公告)日：2024-06-11

申请号：US18118115

申请日：2023-03-06

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/7834 ,  H01L29/785

摘要： A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US11923251B2

公开(公告)日：2024-03-05

申请号：US17314804

申请日：2021-05-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsu-Hsiu Perng ,  Kai-Chieh Yang ,  Zhi-Chang Lin ,  Teng-Chun Tsai ,  Wei-Hao Wu

IPC分类号： H01L21/8238 ,  C23C16/04 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823842 ,  C23C16/042 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/76829 ,  H01L21/823821 ,  H01L29/4941 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

摘要： A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

公开(公告)号：US20230360932A1

公开(公告)日：2023-11-09

申请号：US18303833

申请日：2023-04-20

申请人： Samsung Electronics Co., Ltd.

发明人： Dohyung KIM

IPC分类号： H01L21/67 ,  H01L29/40 ,  H01L21/28 ,  H01L21/311 ,  H01J37/32

CPC分类号： H01L21/67069 ,  H01L29/401 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/31116 ,  H01J37/32724 ,  H01J2237/3387 ,  H01J2237/327

摘要： A method of fabricating an electrode structure may include forming a first gate electrode, performing a removal process on an electrode capping layer formed on the first gate electrode, forming a second gate electrode on the first gate electrode, and nitridating an upper portion of the second gate electrode.

公开(公告)号：US10084086B2

公开(公告)日：2018-09-25

申请号：US15429194

申请日：2017-02-10

申请人： Shanghai Huali Microelectronics Corporation

发明人： Qiuming Huang

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/167 ,  H01L27/11

CPC分类号： H01L29/7848 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636

摘要： A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.

公开(公告)号：US20180211886A1

公开(公告)日：2018-07-26

申请号：US15872306

申请日：2018-01-16

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Qingchun Zhang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L21/823857 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a high dielectric constant (high-k) gate dielectric layer on the semiconductor substrate, the high-k gate dielectric layer including a nitrided surface that has been subjected to a nitriding treatment or an oxidized surface that has been subjected to an oxidizing treatment, forming a metal gate on the nitrided surface of the high-k gate dielectric layer to form an NMOS transistor, or forming a metal gate on the oxidized surface of the high-k gate dielectric layer to form a PMOS transistor.

公开(公告)号：US09991357B2

公开(公告)日：2018-06-05

申请号：US15186982

申请日：2016-06-20

申请人： Samsung Electronics Co., Ltd.

发明人： Jaeyeol Song ,  Wandon Kim ,  Hoonjoo Na ,  Suyoung Bae ,  Hyeok-Jun Son ,  Sangjin Hyun

IPC分类号： H01L27/088 ,  H01L29/51 ,  H01L27/085 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

公开(公告)号：US20180130662A1

公开(公告)日：2018-05-10

申请号：US15865758

申请日：2018-01-09

申请人： Texas Instruments Incorporated

发明人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC分类号： H01L21/28 ,  C23C16/455 ,  C23C16/458 ,  H01J37/32 ,  H01L29/51 ,  H01L21/02

CPC分类号： H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US20170358483A1

公开(公告)日：2017-12-14

申请号：US15621120

申请日：2017-06-13

申请人： Applied Materials, Inc.

发明人： Susmit Singha Roy ,  Yihong Chen ,  Kelvin Chan ,  Abhijit Basu Mallick ,  Srinivas Gandikota

IPC分类号： H01L21/762 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/43 ,  H01L21/32

CPC分类号： H01L21/76229 ,  H01L21/28202 ,  H01L21/32 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/43

摘要： Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause growth of the film from the at least one feature. Methods of forming self-aligned vias are also described.

公开(公告)号：US09806161B1

公开(公告)日：2017-10-31

申请号：US15092910

申请日：2016-04-07

申请人： GLOBALFOUNDRIES INC.

发明人： Shahrukh A. Khan ,  Unoh Kwon ,  Shahab Siddiqui ,  Sean M. Polvino ,  Joseph F. Shepard, Jr.

IPC分类号： H01L29/423 ,  H01L21/311 ,  H01L29/51 ,  H01L21/033 ,  H01L21/84 ,  H01L21/027 ,  H01L21/8234 ,  H01L27/12

CPC分类号： H01L29/42364 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/28202 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1207 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

摘要： One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.