公开(公告)号：US07917881B1

公开(公告)日：2011-03-29

申请号：US11725188

申请日：2007-03-15

申请人： Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

发明人： Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/84

摘要： Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

摘要翻译： 公开了改进电路设计的时序和/或产量。 时序和产量改进通常是电路设计中的竞争目标，因为时序改进通常是由减少电容耦合而产生的，而产量改进通常会增加电容耦合。 因此，时序和产量改进之间的权衡是电路设计和/或优化过程的一部分。

公开(公告)号：US20050172252A1

公开(公告)日：2005-08-04

申请号：US10979868

申请日：2004-11-01

申请人： Chih-Liang Cheng ,  Chung-Do Yang ,  Yan Lin ,  Kuo-Feng Liao

发明人： Chih-Liang Cheng ,  Chung-Do Yang ,  Yan Lin ,  Kuo-Feng Liao

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A tool that a user may employ to assemble the components of a circuit in a floor plan design. The tool provides a user interface that displays the placement of blocks in a floor plan design, and the routing of wires among the blocks. When the designer moves the placement of a target block, the user interface automatically moves any adjacent blocks that would impede the movement of the target block and any block that would impede a block moved in response to the movement of the target block. The user interface may also respond to movement of a target block by showing how various features of the circuit will change as a result of the move. Thus, the user interface may show that moving one block closer to another block will create undesired wiring congestion in the circuit. The user interface also may show when moving a block will result in wiring connections that are too long to maintain a desired voltage level. The tool may also automatically move the placement of related blocks as a group, so that various attributes, such as a minimum distance between adjacent blocks, are maintained.

摘要翻译： 用户可以采用的工具，用于在平面图设计中组装电路的部件。 该工具提供了一个用户界面，用于在平面图设计中显示块的位置，并在块之间布线。 当设计者移动目标块的放置时，用户界面自动地移动任何相邻的块，其将阻碍目标块的移动，并且阻止块响应于目标块的移动而移动的块。 用户接口还可以通过显示电路的各种特征如何随着移动的结果而改变而对目标块的移动做出响应。 因此，用户接口可以示出移动一个块更靠近另一个块将在电路中产生不期望的布线拥塞。 当移动块时，用户界面也可能会显示导线连接太长而不能保持所需的电压电平。 工具还可以自动地将相关块的放置移动为一组，使得保持各种属性，例如相邻块之间的最小距离。

公开(公告)号：US07739630B1

公开(公告)日：2010-06-15

申请号：US11725191

申请日：2007-03-15

申请人： Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

发明人： Hsi-Chuan Chen ,  Chih-Liang Cheng ,  Chung-Do Yang ,  Jeong-Tyng Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/84

摘要： Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

摘要翻译： 公开了改进电路设计的时序和/或产量。 时序和产量改进通常是电路设计中的竞争目标，因为时序改进通常是由减少电容耦合而产生的，而产量改进通常会增加电容耦合。 因此，时序和产量改进之间的权衡是电路设计和/或优化过程的一部分。