-
公开(公告)号：US5304994A
公开(公告)日：1994-04-19
申请号：US896529
申请日：1992-06-09
申请人： Craig Heikes
发明人： Craig Heikes
CPC分类号： G06F7/74
摘要： A circuit and a method for providing an indication of the position of a bit having a selected characteristic in an n-bit binary word are disclosed. The n bits of the binary word are arranged into groups of W bits so that each group is input to a fundamental encoder. The position of the bit having the selected characteristic, among each group of W bits is provided as an encoded output. A multiplexer tree provides a single output indicative of the position of the bit having the selected characteristic in the binary word based on the encoded outputs from the encoders.
摘要翻译： 公开了一种用于在n位二进制字中提供具有选定特性的位的位置的指示的电路和方法。 二进制字的n位被布置成W位组，使得每个组被输入到基本编码器。 在每组W位中具有所选特性的位的位置被提供为编码输出。 复用器树基于来自编码器的编码输出，提供表示具有所选特征的位在二进制字中的单个输出。
-
公开(公告)号：US5390134A
公开(公告)日：1995-02-14
申请号：US11447
申请日：1993-01-29
CPC分类号： G06F7/485 , G06F7/49947
摘要： A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function approximately simultaneously with an addition function performed by the carry propagate adder on fraction inputs FA, FB to ultimately derive a resultant fraction FR, thereby eliminating the need for a conventional post-normalize incrementer. The rounding mechanism has a carry select adder and rounding logic network. The rounding logic network communicates with the carry propagate adder and the carry select adder in order to provide rounding information to the carry select adder. The carry select adder and the rounding logic network jointly provide a rounded output, which is then normalized by the normalizer to thereby derive the resultant fraction.
摘要翻译： 舍入装置与浮点处理器的进位传播加法器相关联，以便减少等待时间并提高性能。 舍入机构与分数输入FA，FB上由进位传播加法器执行的加法函数大致同时执行舍入函数，以最终导出合成分数FR，从而消除对常规后归一化增量器的需要。 舍入机制具有进位选择加法器和舍入逻辑网络。 四舍五入逻辑网络与进位传播加法器和进位选择加法器通信，以便向进位选择加法器提供舍入信息。 进位选择加法器和舍入逻辑网络联合提供舍入输出，然后由归一化器对其进行归一化，从而导出所得分数。
-
公开(公告)号：US06421823B1
公开(公告)日：2002-07-16
申请号：US08549078
申请日：1995-10-27
申请人： Craig Heikes
发明人： Craig Heikes
IPC分类号： G06F1500
CPC分类号： G06F17/5022
摘要： A communications socket between a logic simulator and a system for generating input stimuli based on the current state of the logic simulator is provided. Input stimuli to the logic simulator for use in implementing a particular circuit design simulation are calculated by interfacing an input program which models the function of the circuit being designed with the logic simulator. The lines in this input program are converted by an adaptive vector generator into communications signals which are understandable by the logic simulator so that the desired simulation may take place. The input program thus enables the adaptive vector generator to behaviorally model complex logical systems that the logic simulator model is only a part of and allows for more accurate and detailed simulation. The adaptive vector generator does this by determining the next input vector state in accordance with the present state of the logic simulator model as received from the communications socket. In other words, based on the state data received from the logic simulator, the adaptive vector generation automatically calculates the next stimulus pattern for the logic simulator model and provides this stimuli to the logic simulator through the communications socket. This technique removes the tediousness of the prior art techniques in that the design engineer no longer needs to specify every input step and to anticipate the output state of the circuit.
摘要翻译： 提供了逻辑模拟器和用于基于逻辑模拟器的当前状态产生输入刺激的系统之间的通信插座。 用于实现特定电路设计仿真的逻辑模拟器的输入刺激是通过将所设计的电路的功能与逻辑模拟器建模的输入程序进行接口来计算的。 该输入程序中的线路由自适应矢量发生器转换为通过逻辑模拟器可以理解的通信信号，从而可以进行所需的仿真。 因此，输入程序使得自适应矢量发生器能够对复杂的逻辑系统进行行为建模，逻辑模拟器模型只是其中一部分，并允许更准确和详细的模拟。 自适应向量生成器通过根据从通信套接字接收到的逻辑模拟器模型的当前状态来确定下一个输入向量状态来实现。 换句话说，基于从逻辑模拟器接收到的状态数据，自适应向量生成自动计算逻辑模拟器模型的下一个刺激模式，并通过通信插座将该刺激提供给逻辑模拟器。 这种技术消除了现有技术的繁琐，因为设计工程师不再需要指定每个输入步骤并且预测电路的输出状态。
-
-
搜索结果
3 条记录 (耗时 0.01 秒)
