METHOD OF TIMING CRITICALITY CALCULATION FOR STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUIT
    1.
    发明申请
    METHOD OF TIMING CRITICALITY CALCULATION FOR STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUIT 有权
    定时关键度计算方法对VLSI电路的统计时序优化

    公开(公告)号:US20100242006A1

    公开(公告)日:2010-09-23

    申请号:US12474547

    申请日:2009-05-29

    IPC分类号: G06F17/10

    CPC分类号: G06F17/5031 G06F17/505

    摘要: Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.

    摘要翻译: 提供了一种优化积分电路的统计定时的方法,该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化,以ADD操作和基于块的统计静态的MAX操作 时序分析(SSTA)方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值,计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此,基于统计静态时序分析(SSTA)的ADD操作和MAX操作的线性近似来计算定时收益关键性,因此计算复杂度相对于总节点数是线性的,关键节点显着影响定时收益 可以更准确地提取电路。

    Method of timing criticality calculation for statistical timing optimization of VLSI circuit
    2.
    发明授权
    Method of timing criticality calculation for statistical timing optimization of VLSI circuit 有权
    VLSI电路统计时序优化的定时临界计算方法

    公开(公告)号:US08046724B2

    公开(公告)日:2011-10-25

    申请号:US12474547

    申请日:2009-05-29

    IPC分类号: G06F9/455 G06F17/50

    CPC分类号: G06F17/5031 G06F17/505

    摘要: Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.

    摘要翻译: 提供了一种优化集成电路的统计定时的方法,该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化,以ADD操作和基于块的统计静态的MAX操作 时序分析(SSTA)方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值,计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此,基于统计静态时序分析(SSTA)的ADD操作和MAX操作的线性近似来计算定时收益关键性,因此计算复杂度相对于总节点数是线性的,关键节点显着影响定时收益 可以更准确地提取电路。