公开(公告)号：US08046724B2

公开(公告)日：2011-10-25

申请号：US12474547

申请日：2009-05-29

申请人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

发明人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505

摘要： Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.

摘要翻译： 提供了一种优化集成电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作 时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益 可以更准确地提取电路。

公开(公告)号：US20100242006A1

公开(公告)日：2010-09-23

申请号：US12474547

申请日：2009-05-29

申请人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

发明人： Hyoun Soo Park ,  Young Hwan Kim ,  Dai Joon Hyun ,  Wook Kim

IPC分类号： G06F17/10

CPC分类号： G06F17/5031 ,  G06F17/505

摘要： Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.

摘要翻译： 提供了一种优化积分电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作 时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益 可以更准确地提取电路。

公开(公告)号：US07961028B2

公开(公告)日：2011-06-14

申请号：US12639188

申请日：2009-12-16

申请人： Jiyeon An ,  Young Hwan Kim ,  Hyoun Soo Park

发明人： Jiyeon An ,  Young Hwan Kim ,  Hyoun Soo Park

IPC分类号： H03L5/00

CPC分类号： H03K19/018571

摘要： The present invention relates to a level converter used in a multiple supply voltage system that is required to design a low-power and high-performance semiconductor, and more particularly, to a single supply pass gate level converter (SPLC) for a multiple supply voltage system, which has low power consumption, operates at high speed, and uses only a single supply voltage. The SPLC includes an input data providing circuit unit which receives an input signal of a low supply voltage; a data inversion circuit unit which receives input data from the input data providing circuit unit and outputs inversed input data; a feedback circuit unit which is fed back by an output of the data inversion circuit unit; and a data output buffer which inverses an output of the data inversion circuit unit and outputs an inversed signal. The input data providing circuit unit, the data inversion circuit unit, the feedback circuit unit, and the data output buffer are all driven by a high supply voltage such that only a single supply voltage which is the high supply voltage is required.

摘要翻译： 本发明涉及一种用于设计低功率和高性能半导体所需的多电源电压系统中的电平转换器，更具体地说，涉及一种用于多电源电压的单电源通过门电平转换器（SPLC） 系统功耗低，运行速度快，仅使用单电源电压。 SPLC包括输入数据提供电路单元，其接收低电源电压的输入信号; 数据反转电路单元，其从输入数据提供电路单元接收输入数据并输出反相输入数据; 反馈电路单元，由数据反转电路单元的输出反馈; 以及数据输出缓冲器，其反转数据反转电路单元的输出并输出反相信号。 输入数据提供电路单元，数据反转电路单元，反馈电路单元和数据输出缓冲器均由高电源电压驱动，使得仅需要作为高电源电压的单个电源电压。

公开(公告)号：US20100156371A1

公开(公告)日：2010-06-24

申请号：US12639188

申请日：2009-12-16

申请人： Jiyeon An ,  Young Hwan Kim ,  Hyoun Soo Park

发明人： Jiyeon An ,  Young Hwan Kim ,  Hyoun Soo Park

IPC分类号： G05F1/10

CPC分类号： H03K19/018571

摘要： The present invention relates to a level converter used in a multiple supply voltage system that is required to design a low-power and high-performance semiconductor, and more particularly, to a single supply pass gate level converter (SPLC) for a multiple supply voltage system, which has low power consumption, operates at high speed, and uses only a single supply voltage. The SPLC includes an input data providing circuit unit which receives an input signal of a low supply voltage; a data inversion circuit unit which receives input data from the input data providing circuit unit and outputs inversed input data; a feedback circuit unit which is fed back by an output of the data inversion circuit unit; and a data output buffer which inverses an output of the data inversion circuit unit and outputs an inversed signal. The input data providing circuit unit, the data inversion circuit unit, the feedback circuit unit, and the data output buffer are all driven by a high supply voltage such that only a single supply voltage which is the high supply voltage is required.

摘要翻译： 本发明涉及一种用于设计低功率和高性能半导体所需的多电源电压系统中的电平转换器，更具体地说，涉及一种用于多电源电压的单电源通过门电平转换器（SPLC） 系统功耗低，运行速度快，仅使用单电源电压。 SPLC包括输入数据提供电路单元，其接收低电源电压的输入信号; 数据反转电路单元，其从输入数据提供电路单元接收输入数据并输出反相输入数据; 反馈电路单元，由数据反转电路单元的输出反馈; 以及数据输出缓冲器，其反转数据反转电路单元的输出并输出反相信号。 输入数据提供电路单元，数据反转电路单元，反馈电路单元和数据输出缓冲器均由高电源电压驱动，使得仅需要作为高电源电压的单个电源电压。

公开(公告)号：US06416648B1

公开(公告)日：2002-07-09

申请号：US09696015

申请日：2000-10-26

申请人： Hyoun Soo Park

发明人： Hyoun Soo Park

IPC分类号： C25D356

CPC分类号： C25D3/565

摘要： The present invention relates to a method to manufacture steel sheets coated with Zn—Fe alloy with an excellent corrosion resistance used in producing a body frame and a chassis of an automobile under optimal coating conditions by adjusting the temperature, pH, electric current density of an electrolyte consisting of zinc sulfate hydrate, iron sulfate hydrate, ammonium sulfate and potassium chloride as well as the thickness of a coating layer.

摘要翻译： 本发明涉及通过调节温度，pH，电流密度等方法，在最佳涂布条件下制造具有优异耐腐蚀性的钢板的制造方法。 由硫酸锌水合物，硫酸铁水合物，硫酸铵和氯化钾组成的电解质以及涂层的厚度。