摘要:
A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要:
A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.
摘要:
A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要:
In a fully digital telephone switching system, a digital switch may serve a number of PCM sub systems each having separate forward and reverse highways and each serving a number of subscribers' lines. The highways are grouped in blocks of eight, from which intelligence is received in serial byte-interleaved form and converted by serial-parallel converters to parallel byte-interleaved form. While in this form they are switched to other channels and applied to a super-multiplexer which they leave in parallel byte-interleaved form from which they are restored by another converter to serial byte-interleaved form for application to the switch's outputs. For the reverse channel the arrangement is the reverse of the above, i.e. serial-parallel conversion, switching and parallel-serial conversion to the line multiplex highways. For local calls a loop-back connection is provided via a fixed delay of half a frame time. Thus, if the outputs fail, the arrangement can still handle local calls. Further it is usable on its own as a small exchange.